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기능 16-MBIT (1 MBIT x 16/ 2 MBIT x 8) SYNCHRONOUS FLASH MEMORY
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E28F016XS20 데이터시트, 핀배열, 회로
E
28F016XS
16-MBIT (1 MBIT x 16, 2 MBIT x 8)
SYNCHRONOUS FLASH MEMORY
n Effective Zero Wait-State Performance
up to 33 MHz
Synchronous Pipelined Reads
n SmartVoltage Technology
User-Selectable 3.3V or 5V VCC
User-Selectable 5V or 12V VPP
n 0.33 MB/sec Write Transfer Rate
n Configurable x8 or x16 Operation
n 56-Lead TSOP and SSOP Type I
Package
n Backwards-Compatible with 28F008SA
Command-Set
n 2 µA Typical Deep Power-Down
n 1 mA Typical Active ICC Current in
Static Mode
n 16 Separately-Erasable/Lockable
128-Kbyte Blocks
n 1 Million Erase Cycles per Block
n State-of-the-Art 0.6 µm ETOX™ IV Flash
Technology
Intel’s 28F016XS 16-Mbit flash memory is a revolutionary architecture which is the ideal choice for designing
truly revolutionary high-performance products. Combining very high read performance with the intrinsic
nonvolatility of flash memory, the 28F016XS eliminates the traditional redundant memory paradigm of
shadowing code from a slow nonvolatile storage source to a faster execution memory, such as DRAM, for
improved system performance. The innovative capabilities of the 28F016XS enable the design of direct-
execute code and mass storage data/file flash memory systems.
The 28F016XS is the highest performance high-density nonvolatile read/program flash memory solution
available today. Its synchronous pipelined read interface, flexible VCC and VPP voltages, extended cycling,
fast program and read performance, symmetrically-blocked architecture, and selective block locking provide a
highly flexible memory component suitable for resident flash component arrays on the system board or
SIMMs. The synchronous pipelined interface and x8/x16 architecture of the 28F016XS allow easy interface
with minimal glue logic to a wide range of processors/buses, providing effective zero wait-state read
performance up to 33 MHz. The 28F016XS’s dual read voltage allows the same component to operate at
either 3.3V or 5.0V VCC. Programming voltage at 5V VPP minimizes external circuitry in minimal-chip, space
critical designs, while the 12.0V VPP option maximizes program/erase performance. Its high read performance
combined with flexible block locking enable both storage and execution of operating systems/application
software and fast access to large data tables. The 28F016XS is manufactured on Intel’s 0.6 µm ETOX IV
process technology.
November 1996
Order Number: 290532-004




E28F016XS20 pdf, 반도체, 판매, 대치품
28F016XS FLASH MEMORY
E
Number
-001
-002
-003
REVISION HISTORY
Description
Original Version
Removed support of the following features:
All page buffer operations (read, write, programming, Upload Device Information)
Command queuing
Software Sleep and Abort
Erase all Unlocked Blocks and Two-Byte Write
RY/BY# Configuration as part of the Device Configuration command
Changed definition of “NC.” Removed “No internal connection to die” from description.
Added “xx” to Upper Byte of Command (Data) Definition in Sections 4.3 and 4.4.
Modified parameters “V” and “I” of Section 5.1 to apply to “NC” pins.
Increased IPPR (VPP Read Current) for VPP > VCC to 200 µA at VCC = 3.3V/5.0V.
Changed VCC = 5.0V DC Characteristics (Section 5.5) marked with Note 1 to indicate
that these currents are specified for a CMOS rise/fall time (10% to 90%) of <5 ns
and a TTL rise/fall time of <10 ns.
Corrected tPHCH (RP# High to CLK) to be a “Min” specification at VCC = 3.3V/5.0V.
Corrected the graphical representation of tWHCH and tEHCH in Figures 15 and 16.
Increased Typical “Byte/Word Program Times” (tWHRH1A/tWHRH1B) for VPP = 5.0V (Sec.
5.13): tWHRH1A from 16.5 µs to 29.0 µs and tWHRH1B from 24.0 µs to 35.0 µs at VCC =
3.3V
tWHRH1A from 11.0 µs to 20.0 µs and tWHRH1B from 16.0 µs to 25.0 µs at VCC = 5.0V.
Increased Typical “Block Program Times” (tWHRH2/ tWHRH3) for VPP = 5.0V (Section 5.13):
tWHRH2 from 2.2 sec to 3.8 sec and tWHRH3 from 1.6 sec to 2.4 sec at VCC = 3.3V
tWHRH2 from 1.6 sec to 2.8 sec and tWHRH3 from 1.2 sec to 1.7 sec at VCC = 5.0V.
Changed “Time from Erase Suspend Command to WSM Ready” spec name to “Erase
Suspend Latency Time to Read;” Modified typical values and Added Min/Max values
at VCC =3.3/5.0V and VPP =5.0/12.0V (Section 5.13).
Minor cosmetic changes throughout document.
Added 3/5# pin to Pinout Configuration (Figure 2), Product Overview (Section 1.1) and
Lead Descriptions (Section 2.1)
Modified Block Diagram (Figure 1): Removed Address Counter; Added 3/5# pin
Added 3/5# pin to Test Conditions of ICCS Specifications
Added 3/5# pin (Y) to Timing Nomenclature (Section 5.6)
Removed Note 7 of Section 5.7
Modified Device Configuration Code: Incorporated RY/BY# Configuration (Level Mode
support ONLY)
Modified Power-Up and Reset Timings (Section 5.10) to include 3/5# pin: Removed t5VPH
and t3VPH specifications; Added tPLYL, tPLYH, tYLPH, and tYHPH specifications
Added SSOP pinout (Figure 2) and Mechanical Specifications
Corrected TSOP Mechanical Specification A1 from 0.50 mm to 0.050 mm (Section 6.0)
Minor cosmetic changes throughout document.
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E28F016XS20 전자부품, 판매, 대치품
E
28F016XS FLASH MEMORY
1.0 INTRODUCTION
The documentation of the Intel 28F016XS Flash
memory device includes this datasheet, a detailed
user’s manual, a number of application notes and
design tools, all of which are referenced in
Appendix B.
The datasheet is intended to give an overview of
the chip feature-set and of the operating AC/DC
specifications. The 16-Mbit Flash Product Family
User’s Manual provides complete descriptions of
the user modes, system interface examples and
detailed descriptions of all principles of operation. It
also contains the full list of software algorithm
flowcharts, and a brief section on compatibility with
the Intel 28F008SA.
Significant 28F016XS feature revisions occurred
between datasheet revisions 290532-001 and
290532-002. These revisions center around
removal of the following features:
All page buffer operations (read, write,
programming, Upload Device Information)
Command queuing
Software Sleep and Abort
Erase all Unlocked Blocks and Two-Byte Write
RY/BY# Configuration options
In addition, a significant 28F016XS change
occurred between datasheet revisions 290532-002
and 290532-003. This change centers around the
addition of a 3/5# pin to the device’s pinout
configuration. Figures 2 and 3 show the 3/5# pin
assignment for the TSOP and SSOP Type I
packages.
Intel recommends that all customers obtain the
latest revisions of 28F016XS documentation.
1.1 Product Overview
The 28F016XS is a high-performance, 16-Mbit
(16,777,216-bit) block erasable nonvolatile random
access memory organized as either 1 Mword x 16
or 2 Mbyte x 8, subdivided into even and odd
banks. Address A1 makes the bank selection. The
28F016XS includes sixteen 128-Kbyte (131,072
byte) blocks or sixteen 64-Kword (65,536 word)
blocks. Chip memory maps for x8 and x16 modes
are shown in Figures 4 and 5.
The implementation of a new architecture, with
many enhanced features, will improve the device
operating characteristics and result in greater
product reliability and ease-of-use as compared to
other flash memories. Significant features of the
28F016XS as compared to previous asynchronous
flash memories include:
Synchronous Pipelined Read Interface
Significantly Improved Read and Program
Performance
SmartVoltage Technology
Selectable 3.3V or 5.0 VCC
Selectable 5.0V or 12.0 VPP
Block Program/Erase Protection
The 28F016XS’s synchronous pipelined interface
dramatically raises read performance far beyond
previously attainable levels. Addresses are
synchronously latched and data is read from a
28F016XS bank every 30 ns (5V VCC, SFI
Configuration = 2). This capability translates to zero
wait-state reads at clock rates up to 33 MHz at 5V
VCC, after an initial address pipeline fill delay and
assuming even and odd banks within the flash
memory are alternately accessed. Data is latched
and driven valid 20 ns (tCHQV) after a rising CLK
edge. The 28F016XS is capable of operating up to
50 MHz (5V VCC); its programmable SFI
Configuration enables system design flexibility,
optimizing the 28F016XS to a specific system clock
frequency. See Section 4.9, SFI Configuration
Table, for specific SFI Configurations for given
operating frequencies.
The SFI Configuration optimizes the 28F016XS for
a wide range of system operating frequencies. The
default SFI Configuration is 4, which allows system
boot from the 28F016XS at any frequency up to
50 MHz at 5V VCC. After initiating an access, data
is latched and begins driving on the data outputs
after a CLK count corresponding to the SFI
Configuration has elapsed. The 28F016XS will hold
data valid until CE# or OE# is deactivated or a CLK
count corresponding to the SFI Configuration for a
subsequent access has elapsed.
The CLK and ADV# inputs, new to the 28F016XS in
comparison to previous flash memories, control
address latching and device synchronization during
read operations. The CLK input controls the device
latencies, times out the SFI Configuration counter
and synchronizes data outputs. ADV# indicates the
presence of a valid address on the 28F016XS
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E28F016XS20

16-MBIT (1 MBIT x 16/ 2 MBIT x 8) SYNCHRONOUS FLASH MEMORY

Intel Corporation
Intel Corporation

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