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E28F200BL-T150 데이터시트 PDF




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기능 2-MBIT (128K x 16/ 256K x 8)LOW-POWER BOOT BLOCK FLASH MEMORY FAMILY
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E28F200BL-T150 데이터시트, 핀배열, 회로
2-MBIT (128K x 16 256K x 8)
LOW-POWER BOOT BLOCK
FLASH MEMORY FAMILY
28F200BL-T B 28F002BL-T B
Y Low Voltage Operation for Very Low
Power Portable Applications
VCC e 3 0V – 3 6V
Y Expanded Temperature Range
b20 C to a70 C
Y x8 x16 Input Output Architecture
28F200BL-T 28F200BL-B
For High Performance and High
Integration 16-bit and 32-bit CPUs
Y x8-only Input Output Architecture
28F002BL-T 28F002BL-B
For Space Constrained 8-bit
Applications
Y Upgradeable to Intel’s SmartVoltage
Products
Y Optimized High-Density Blocked
Architecture
One 16-KB Protected Boot Block
Two 8-KB Parameter Blocks
One 96-KB Main Block
One 128-KB Main Block
Top or Bottom Boot Locations
Y Extended Cycling Capability
10 000 Block Erase Cycles
Y Automated Word Byte Write and Block
Erase
Command User Interface
Status Registers
Erase Suspend Capability
Y SRAM-Compatible Write Interface
Y Automatic Power Savings Feature
0 8 mA Typical ICC Active Current in
Static Operation
Y Very High-Performance Read
150 ns Maximum Access Time
65 ns Maximum Output Enable Time
Y Low Power Consumption
15 mA Typical Active Read Current
Y Reset Deep Power-Down Input
0 2 mA ICC Typical
Acts as Reset for Boot Operations
Y Write Protection for Boot Block
Y Hardware Data Protection Feature
Erase Write Lockout during Power
Transitions
Y Industry Standard Surface Mount
Packaging
28F200BL JEDEC ROM Compatible
44-Lead PSOP
56-Lead TSOP
28F002BL 40-Lead TSOP
Y 12V Word Byte Write and Block Erase
VPP e 12V g5% Standard
Y ETOXTM III Flash Technology
3 3V Read
Y Independent Software Vendor Support
Other brands and names are the property of their respective owners
Information in this document is provided in connection with Intel products Intel assumes no liability whatsoever including infringement of any patent or
copyright for sale and use of Intel products except as provided in Intel’s Terms and Conditions of Sale for such products Intel retains the right to make
changes to these specifications at any time without notice Microcomputer Products may have minor variations to this specification known as errata
COPYRIGHT INTEL CORPORATION 1995
December 1995
Order Number 290449-006




E28F200BL-T150 pdf, 반도체, 판매, 대치품
28F200BL-T B 28F002BL-T B
Program and Erase Automation allow program
and erase operations to be executed using a two-
write command sequence to the CUI The internal
Write State Machine (WSM) automatically executes
the algorithms and timings necessary for program
and erase operations including verifications there-
by unburdening the microprocessor or microcontrol-
ler Writing of memory data is performed in word or
byte increments for the 28F200BL family and in byte
increments for the 28F002BL family typically within
11 ms
The Status Register (SR) indicates the status of the
WSM and whether the WSM successfully completed
the desired program or erase operation
Maximum Access Time of 150 ns (tACC) is achieved
over the commercial temperature range (0 C to
a70 C) over VCC supply voltage range (3 0V to
3 6V 4 5V to 5 5V) and 50 pF output load
IPP Program current is 40 mA for x16 operation
and 30 mA for x8 operation IPP Erase current is
30 mA maximum VPP erase and programming
voltage is 11 4V to 12 6V (VPP e 12V g5%) un-
der all operating conditions
Typical ICC Active Current of 15 mA is achieved
for the x16 products and the x8 products
The 2-Mbit flash family is also designed with an Au-
tomatic Power Savings (APS) feature to minimize
system battery current drain and allow for extremely
low power designs Once the device is accessed to
read the array data APS mode will immediately put
the memory in static mode of operation where ICC
active current is typically 0 8 mA until the next read
is initiated
When the CE and RP pins are at VCC and the
BYTE pin (28F200BL-only) is at either VCC or GND
the CMOS Standby mode is enabled where ICC is
typically 40 mA
A Deep Power-down Mode is enabled when the
RP pin is at ground minimizing power consumption
and providing write protection during power-up con-
ditions ICC current during deep power-down mode
is 0 20 mA typical An initial maximum access time
or Reset Time of 600 ns is required from RP
switching until outputs are valid Equivalently the
device has a maximum wake-up time of 1 ms until
writes to the Command User Interface are recog-
nized When RP is at ground the WSM is reset the
Status Register is cleared and the entire device is
protected from being written to This feature pre-
vents data corruption and protects the code stored
in the device during system reset The system Reset
pin can be tied to RP to reset the memory to nor-
mal read mode upon activation of the Reset pin
When the CPU enters reset mode it expects to read
the contents of a memory location Furthermore
with on-chip program erase automation in the
2-Mbit family and the RP functionality for data pro-
tection after the CPU is reset and even if a program
or erase command is issued the device will not rec-
ognize any operation until RP returns to its normal
state
For the 28F200BL Byte-wide or Word-wide In-
put Output Control is possible by controlling the
BYTE pin When the BYTE pin is at a logic low
the device is in the byte-wide mode (x8) and data is
read and written through DQ 0 7 During the byte-
wide mode DQ 8 14 are tri-stated and DQ15 Ab1
becomes the lowest order address pin When the
BYTE pin is at a logic high the device is in the
word-wide mode (x16) and data is read and written
through DQ 0 15
1 3 Applications
The 2-Mbit low power boot block flash memory fami-
ly combines high density 3V operation high per-
formance cost-effective flash memories with block-
ing and hardware protection capabilities Its flexibility
and versatility will reduce costs throughout the prod-
uct life cycle Flash memory is ideal for Just-In-Time
production flow reducing system inventory and
costs and eliminating component handling during
the production phase During the product life cycle
when code updates or feature enhancements be-
come necessary flash memory will reduce the up-
date costs by allowing either a user-performed code
change via floppy disk or a remote code change via
a serial link The 2-Mbit boot block flash memory
family provides full function blocked flash memories
suitable for a wide range of applications These ap-
plications include Extended PC BIOS Handy Digi-
tal Cellular Phone program and data storage and
various other portable embedded applications where
both program and data storage are required
Reprogrammable systems such as Notebook and
Palmtop computers are ideal applications for the
2-Mbit low power flash products Portable and han-
dheld personal computer applications are becoming
more complex with the addition of power manage-
ment software to take advantage of the latest micro-
processor technology the availability of ROM-based
application software pen tablet code for electronic
handwriting and diagnostic code Figure 1 shows an
example of a 28F200BL-T application
This increase in software sophistication augments
the probability that a code update will be required
after the PC is shipped The 2-Mbit low power flash
memory products provide an inexpensive update so-
4

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E28F200BL-T150 전자부품, 판매, 대치품
28F200BL-T B 28F002BL-T B
Figure 4 TSOP Lead Configuration for x8 x16 28F200BL
290449 – 4
Figure 5 TSOP Lead Configuration for x8 28F002BL
290449 – 5
7

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E28F200BL-T150

2-MBIT (128K x 16/ 256K x 8)LOW-POWER BOOT BLOCK FLASH MEMORY FAMILY

Intel Corporation
Intel Corporation

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