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부품번호 E28F800B5B90 기능
기능 SMART 5 BOOT BLOCK FLASH MEMORY FAMILY 2/ 4/ 8 MBIT
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E28F800B5B90 데이터시트, 핀배열, 회로
E
ADVANCE INFORMATION
SMART 5 BOOT BLOCK
FLASH MEMORY FAMILY
2, 4, 8 MBIT
28F200B5, 28F400B5, 28F800B5, 28F004B5
n SmartVoltage Technology
Smart 5 Flash: 5 V Reads,
5 V or 12 V Writes
Increased Programming Throughput
at 12 V VPP
n Very High-Performance Read
2-, 4-Mbit: 60 ns Access Time
8-Mbit: 70 ns Access Time
n x8 or x8/x16-Configurable Data Bus
n Low Power Consumption
Max 60 mA Read Current at 5 V
Auto Power Savings: <1 mA Typical
Standby Current
n Optimized Array Blocking Architecture
16-KB Protected Boot Block
Two 8-KB Parameter Blocks
96-KB and 128-KB Main Blocks
Top or Bottom Boot Locations
n Extended Temperature Operation
–40 °C to +85 °C
n Industry-Standard Packaging
40, 48-Lead TSOP, 44-Lead PSOP
n Extended Block Erase Cycling
100,000 Cycles at Commercial Temp
10,000 Cycles at Extended Temp
n Hardware Data Protection Feature
Absolute Hardware-Protection for
Boot Block
Write Lockout during Power
Transitions
n Automated Word/Byte Program and
Block Erase
Command User Interface
Status Registers
Erase Suspend Capability
n SRAM-Compatible Write Interface
n Reset/Deep Power-Down Input
Provides Low-Power Mode and
Reset for Boot Operations
n Pinout Compatible 2, 4, and 8 Mbit
n ETOX™ Flash Technology
0.6 µ ETOX IV Initial Production
0.4 µ ETOX V Later Production
Intel’s Smart 5 boot block flash memory family provides 2-, 4-, and 8-Mbit memories featuring high-density,
low-cost, nonvolatile, read/write storage solutions for a wide range of applications. Their asymmetrically-
blocked architecture, flexible voltage, and extended cycling provide highly flexible components suitable for
embedded code execution applications, such as networking infrastructure and office automation.
Based on Intel’s boot block architecture, the Smart 5 boot block memory family enables quick and easy
upgrades for designs that demand state-of-the-art technology. This family of products comes in industry-
standard packages: the 40-lead TSOP for very space-constrained 8-bit applications, 48-lead TSOP, ideal for
board-constrained higher-performance 16-bit applications, and the rugged, easy to handle 44-lead PSOP.
December 1997
Order Number: 290599-004




E28F800B5B90 pdf, 반도체, 판매, 대치품
SMART 5 BOOT BLOCK MEMORY FAMILY
E
Number
-001
-002
-003
-004
REVISION HISTORY
Description
Original Version
Minor changes throughout document.
Section 3.1.5 and Figure 14 redone to clarify program/erase operation abort.
Information added to Table 2, Figure 1, and Section 3.3 to clarify WP# on 8-Mbit,
44-PSOP.
Read and Write Waveforms changed to numbered format.
Typical numbers removed from DC Characteristics and Erase/Program Timings.
Minor text changes throughout document.
Figure 1, 44-PSOP pinout: mistake on pin 3 on 2-Mbit pinout corrected from A17 to NC.
Specs tEHQZ and tGHQZ improved.
Explanations of program/erase abort commands reworked in Table 6, Command
Codes.
Specifications for 28F004B5 40-TSOP version added; Erase suspend text and
flowchart updated for clarity (Section 3.2.5.1, Table 6, Figure 10)
4 ADVANCE INFORMATION

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E28F800B5B90 전자부품, 판매, 대치품
E
SMART 5 BOOT BLOCK MEMORY FAMILY
Symbol
A0–A18
A9
DQ0–DQ7
DQ8–DQ15
CE#
OE#
WE#
RP#
Table 2. Pin Descriptions
Type
INPUT
INPUT
Name and Function
ADDRESS INPUTS for memory addresses. Addresses are internally latched
during a write cycle.
28F200: A[0–16], 28F400: A[0–17], 28F800: A[0–18], 28F004: A[0–18]
ADDRESS INPUT: When A9 is at VHH the signature mode is accessed. During
this mode, A0 decodes between the manufacturer and device IDs. When BYTE#
is at a logic low, only the lower byte of the signatures are read. DQ15/A–1 is a
don’t care in the signature mode when BYTE# is low.
INPUT/
OUTPUT
DATA INPUTS/OUTPUTS: Inputs array data on the second CE# and WE# cycle
during a Program command. Inputs commands to the Command User Interface
when CE# and WE# are active. Data is internally latched during the write cycle.
Outputs array, intelligent identifier and status register data. The data pins float to
tri-state when the chip is de-selected or the outputs are disabled.
INPUT/
OUTPUT
DATA INPUTS/OUTPUTS: Inputs array data on the second CE# and WE# cycle
during a Program command. Data is internally latched during the write cycle.
Outputs array data. The data pins float to tri-state when the chip is de-selected or
the outputs are disabled as in the byte-wide mode (BYTE# = “0”). In the byte-wide
mode DQ15/A–1 becomes the lowest order address for data output on DQ0–DQ7.
Not applicable to 28F004B5.
INPUT
CHIP ENABLE: Activates the device’s control logic, input buffers, decoders and
sense amplifiers. CE# is active low. CE# high de-selects the memory device and
reduces power consumption to standby levels. If CE# and RP# are high, but not
at a CMOS high level, the standby current will increase due to current flow
through the CE# and RP# input stages.
INPUT OUTPUT ENABLE: Enables the device’s outputs through the data buffers during
a read cycle. OE# is active low.
INPUT
WRITE ENABLE: Controls writes to the command register and array blocks. WE#
is active low. Addresses and data are latched on the rising edge of the WE#
pulse.
INPUT
RESET/DEEP POWER-DOWN: Uses three voltage levels (VIL, VIH, and VHH) to
control two different functions: reset/deep power-down mode and boot block
unlocking. It is backwards-compatible with the BX/BL/BV products.
When RP# is at logic low, the device is in reset/deep power-down mode,
which puts the outputs at High-Z, resets the Write State Machine, and draws
minimum current.
When RP# is at logic high, the device is in standard operation. When RP#
transitions from logic-low to logic-high, the device defaults to the read array mode.
When RP# is at VHH, the boot block is unlocked and can be programmed or
erased. This overrides any control from the WP# input.
ADVANCE INFORMATION
7

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E28F800B5B90

SMART 5 BOOT BLOCK FLASH MEMORY FAMILY 2/ 4/ 8 MBIT

Intel Corporation
Intel Corporation

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