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PDF EBS11RC4ACNA-75 Data sheet ( Hoja de datos )
| Número de pieza | EBS11RC4ACNA-75 | |
| Descripción | 1 GB Registered SDRAM DIMM | |
| Fabricantes | Elpida Memory | |
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DATA SHEET
1 GB Registered SDRAM DIMM
EBS11RC4ACNA (128M words × 72 bits, 2 banks)
Description
Features
The EBS11RC4ACNA is 128M words × 72 bits,
2 banks Synchronous Dynamic RAM Registered
Module, mounted 36 pieces of 256M bits SDRAM
sealed in TCP package. This module provides high
density and large quantities of memory in a small
space without utilizing the surface mounting
technology. Decoupling capacitors are mounted on
power supply line for noise reduction.
Note: Do not push the cover or drop the modules in
order to protect from mechanical defects, which
would be electrical defects.
• Fully compatible with 8 bytes DIMM: JEDEC
standard outline
• 168-pin socket type dual in line memory module
(DIMM)
PCB height: 30.48mm (1.20inch)
Lead pitch: 1.27mm
• 3.3V power supply
• Clock frequency: 133MHz (max.)
• LVTTL interface
• Data bus width: × 72 ECC
• Single pulsed /RAS
• 4 Banks can operates simultaneously and
independently
• Burst read/write operation and burst read/single write
operation capability
• Programmable burst length (BL): 1, 2, 4, 8
• 2 variations of burst sequence
Sequential
Interleave
• Programmable /CAS latency (CL): 2, 3
• Registered inputs with one clock delay
• Byte control by DQMB
• Refresh cycles: 8192 refresh cycles/64ms
• 2 variations of refresh
Auto refresh
Self refresh
• 1 piece of PLL clock driver, 3 pieces of register driver
and 1 piece of serial EEPROM (2k bits) for Presence
Detect (SPD) on PCB.
Document No. E0106E30 (Ver. 3.0)
Date Published June 2002 (K) Japan
URL: http://www.elpida.com
Elpida Memory, Inc. 2001-2002
1 page  
EBS11RC4ACNA
Byte No. Function described
SDRAM access from Clock
26 (3rd highest /CAS latency)
Undefined
Minimum row precharge time
27 (-7A)
(-75)
28 Row active to row active min
/RAS to /CAS delay min
29 (-7A)
(-75)
30 Minimum /RAS pulse width
31 Density of each bank on module
32
33
34
35
36 to 40
41
42 to 61
62
63
64 to 65
66
67 to 71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
Address and command signal input
setup time
Address and command signal input
hold time
Data signal input setup time
Data signal input hold time
Superset information
Minimum bank cycle time
(-7A)
(-75)
Superset information
SPD data revision code
Checksum for bytes 0 to 62
(-7A)
(-75)
Manufacturer’s JEDEC ID code
Manufacturer’s JEDEC ID code
Manufacturer’s JEDEC ID code
Manufacturing location
Manufacturer’s part number
Manufacturer’s part number
Manufacturer’s part number
Manufacturer’s part number
Manufacturer’s part number
Manufacturer’s part number
Manufacturer’s part number
Manufacturer’s part
Manufacturer’s part number
Manufacturer’s part number
Manufacturer’s part number
Manufacturer’s part number
Manufacturer’s part number
Manufacturer’s part number
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Hex value
0 0 0 0 0 0 0 0 00H
0 0 0 0 1 1 1 1 0FH
0 0 0 1 0 1 0 0 14H
0 0 0 0 1 1 1 1 0FH
0 0 0 0 1 1 1 1 0FH
0 0 0 1 0 1 0 0 14H
0 0 1 0 1 1 0 1 2DH
1 0 0 0 0 0 0 0 80H
0 0 0 1 0 1 0 1 15H
0 0 0 0 1 0 0 0 08H
0 0 0 1 0 1 0 1 15H
0 0 0 0 1 0 0 0 08H
0 0 0 0 0 0 0 0 00H
0 0 1 1 1 1 0 0 3CH
0 1 0 0 0 0 1 1 43H
0 0 0 0 0 0 0 0 00H
0 0 0 1 0 0 1 0 12H
1 0 1 1 1 0 0 0 B8H
0 0 0 0 0 0 0 0 00H
0 1 1 1 1 1 1 1 7FH
1 1 1 1 1 1 1 0 FEH
0 0 0 0 0 0 0 0 00H
× × × × × × × × ××
0 1 0 0 0 1 0 1 45H
0 1 0 0 0 0 1 0 42H
0 1 0 1 0 0 1 1 53H
0 0 1 1 0 0 0 1 31H
0 0 1 1 0 0 0 1 31H
0 1 0 1 0 0 1 0 52H
0 1 0 0 0 0 1 1 43H
0 0 1 1 0 1 0 0 34H
0 1 0 0 0 0 0 1 41H
0 1 0 0 0 0 1 1 43H
0 1 0 0 1 1 1 0 4EH
0 1 0 0 0 0 0 1 41H
0 0 1 0 1 1 0 1 2DH
0 0 1 1 0 1 1 1 37H
Comments
15ns
20ns
15ns
15ns
20ns
45ns
2 bank
512M byte
1.5ns*5
0.8ns*5
1.5ns*5
0.8ns*5
Future use
60ns
67.5ns
Future use
Rev. 1.2
184
00
Continuation code
Elpida Memory
*2 (ASCII-8bit code)
E
B
S
1
1
R
C
4
A
C
N
A
—
7
Data Sheet E0106E30 (Ver. 3.0)
5
5 Page 
EBS11RC4ACNA
Relationship Between Frequency and Minimum Latency (SDRAM device specification)
Parameter
-7A -75
Frequency (MHz)
133 133 133 100
tCK (ns)
7.5 7.5 7.5 10
/CAS latency
Active command to column command
(same bank)
Active command to active command
(same bank)
Active command to precharge command
(same bank)
Precharge command to active command
(same bank)
Write recovery or data-in to precharge
command (same bank)
Active command to active command
(different bank)
Self refresh exit time
Last data in to active command
(Auto precharge, same bank)
Symbol
lRCD
lRC
lRAS
lRP
lDPL
lRRD
lSREX
lDAL
CL = 3
2
8
6
2
2
2
1
4
CL = 2
2
8
6
2
2
2
1
4
CL = 3
3
9
6
3
2
2
1
5
CL = 2
2
7
5
2
2
2
1
4
Self refresh exit to command input
lSEC
8
8
9
7
Precharge command to high impedance lHZP
3
2
Last data out to active command
(Auto precharge, same bank)
Last data out to precharge (early
precharge)
Column command to column command
lAPR
lEP
lCCD
1
–2
1
1
–1
1
Write command to data in latency
lWCD
0
0
DQM to data in
lDID 0
0
DQM to data out
lDOD
2
2
CKE to CLK disable
lCLE
1
1
Register set to active command
lMRD
1
1
/CS to command disable
lCDD
0
0
Power down exit to command input
lPEC
1
1
Notes: 1. IRCD to IRRD are recommended value.
2. Be valid [DESL] or [NOP] at next command of self refresh exit.
3. Except [DESL] and [NOP]
3
1
–2
1
0
0
2
1
1
0
1
2
1
–1
1
0
0
2
1
1
0
1
Notes
1
1
1
1
1
1
2
= [lDPL + lRP]
= [lRC]
3
Data Sheet E0106E30 (Ver. 3.0)
11
11 Page | ||
| Páginas | Total 15 Páginas | |
| PDF Descargar | [ Datasheet EBS11RC4ACNA-75.PDF ] | |
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