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부품번호 | EBS11RC4ACNA-7A 기능 |
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기능 | 1 GB Registered SDRAM DIMM | ||
제조업체 | Elpida Memory | ||
로고 | |||
DATA SHEET
1 GB Registered SDRAM DIMM
EBS11RC4ACNA (128M words × 72 bits, 2 banks)
Description
Features
The EBS11RC4ACNA is 128M words × 72 bits,
2 banks Synchronous Dynamic RAM Registered
Module, mounted 36 pieces of 256M bits SDRAM
sealed in TCP package. This module provides high
density and large quantities of memory in a small
space without utilizing the surface mounting
technology. Decoupling capacitors are mounted on
power supply line for noise reduction.
Note: Do not push the cover or drop the modules in
order to protect from mechanical defects, which
would be electrical defects.
• Fully compatible with 8 bytes DIMM: JEDEC
standard outline
• 168-pin socket type dual in line memory module
(DIMM)
PCB height: 30.48mm (1.20inch)
Lead pitch: 1.27mm
• 3.3V power supply
• Clock frequency: 133MHz (max.)
• LVTTL interface
• Data bus width: × 72 ECC
• Single pulsed /RAS
• 4 Banks can operates simultaneously and
independently
• Burst read/write operation and burst read/single write
operation capability
• Programmable burst length (BL): 1, 2, 4, 8
• 2 variations of burst sequence
Sequential
Interleave
• Programmable /CAS latency (CL): 2, 3
• Registered inputs with one clock delay
• Byte control by DQMB
• Refresh cycles: 8192 refresh cycles/64ms
• 2 variations of refresh
Auto refresh
Self refresh
• 1 piece of PLL clock driver, 3 pieces of register driver
and 1 piece of serial EEPROM (2k bits) for Presence
Detect (SPD) on PCB.
Document No. E0106E30 (Ver. 3.0)
Date Published June 2002 (K) Japan
URL: http://www.elpida.com
Elpida Memory, Inc. 2001-2002
EBS11RC4ACNA
Serial PD Matrix*1
Byte No. Function described
0
Number of bytes used by module
manufacturer
1 Total SPD memory size
2 Memory type
3 Number of row addresses bits
4 Number of column addresses bits
5 Number of banks
6 Module data width
7 Module data width (continued)
8 Module interface signal levels
SDRAM cycle time
9 (highest /CAS latency)
7.5ns
SDRAM access from Clock
10 (highest /CAS latency)
5.4ns
11 Module configuration type
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Hex value
1 0 0 0 0 0 0 0 80H
0 0 0 0 1 0 0 0 08H
0 0 0 0 0 1 0 0 04H
0 0 0 0 1 1 0 1 0DH
0 0 0 0 1 0 1 1 0BH
0 0 0 0 0 0 1 0 02H
0 1 0 0 1 0 0 0 48H
0 0 0 0 0 0 0 0 00H
0 0 0 0 0 0 0 1 01H
0 1 1 1 0 1 0 1 75H
0 1 0 1 0 1 0 0 54H
0 0 0 0 0 0 1 0 02H
12 Refresh rate/type
1 0 0 0 0 0 1 0 82H
13 SDRAM width
0 0 0 0 0 1 0 0 04H
14 Error checking SDRAM width 0 0 0 0 0 1 0 0 04H
SDRAM device attributes:
15 minimum clock delay for back-to- 0 0 0 0 0 0 0 1 01H
back random column addresses
16
SDRAM device attributes:
Burst lengths supported
0 0 0 0 1 1 1 1 0FH
17
SDRAM device attributes: number of
banks on SDRAM device
0
0
0
0
0
1
0
0
04H
18
SDRAM device attributes:
/CAS latency
0 0 0 0 0 1 1 0 06H
19
SDRAM device attributes:
/CS latency
20
SDRAM device attributes:
/WE latency
0 0 0 0 0 0 0 1 01H
0 0 0 0 0 0 0 1 01H
21 SDRAM device attributes
0 0 0 1 1 1 1 0 1FH
22 SDRAM device attributes: General 0 0 0 0 1 1 1 0 0EH
SDRAM cycle time
23 (2nd highest /CAS latency)
(-7A) 7.5ns
0 1 1 1 0 1 0 1 75H
(-75) 10ns
1 0 1 0 0 0 0 0 A0H
SDRAM access from Clock
24 (2nd highest /CAS latency)
(-7A) 5.4ns
0 1 0 1 0 1 0 0 54H
(-75) 6ns
0 1 1 0 0 0 0 0 60H
SDRAM cycle time
25 (3rd highest /CAS latency)
Undefined
0 0 0 0 0 0 0 0 00H
Comments
128
256 byte
SDRAM
13
11
2
72 bit
0 (+)
LVTTL
CL = 3*5
ECC
Normal
(7.8125µs)
Self refresh
64M × 4
×4
1 CLK
1, 2, 4, 8
4
2, 3
0
0
Registered
VDD ± 10%
CL = 2*5
Data Sheet E0106E30 (Ver. 3.0)
4
4페이지 EBS11RC4ACNA
Block Diagram
/RCS0
/RCS1
RDQMB0
4 10Ω
DQ0 to DQ3
4 10Ω
DQ4 to DQ7
RDQMB1
4 10Ω
DQ8 to DQ11
4 10Ω
DQ12 to DQ15
CB0 to CB3
/RCS2
/RCS3
RDQMB2
4
10Ω
4 10Ω
DQ16 to DQ19
4 10Ω
DQ20 to DQ23
RDQMB3
4 10Ω
DQ24 to DQ27
4 10Ω
DQ28 to DQ31
/CS0, /CS1, /CS2, /CS3
DQMB0 to DQMB7
BA0 to BA1
A0 to A12
/RAS
/CAS
CKE0
/WE
VDD
REGE
PLL CLK
10kΩ
R
E
G
I
S
T
E
R
DQMB /CS
D0
I/O0
to I/O3
DQMB /CS
D1
I/O0
to I/O3
DQMB /CS
D2
I/O0
to I/O3
DQMB /CS
D3
I/O0
to I/O3
DQMB /CS
D4
I/O0
to I/O3
DQMB /CS
D18
I/O0
to I/O3
RDQMB4
DQ32 to DQ35
4
10Ω
DQMB /CS
D19
I/O0
to I/O3
DQ36 to DQ39
4
DQMB /CS
D20
I/O0
to I/O3
RDQMB5
DQ40 to DQ43
4
10Ω
10Ω
DQMB /CS
D21
I/O0
to I/O3
DQ44 to DQ47
4
10Ω
DQMB /CS
D22
I/O0
to I/O3
10Ω
4
CB4 to CB7
DQMB /CS
D9
I/O0
to I/O3
DQMB /CS
D10
I/O0
to I/O3
DQMB /CS
D11
I/O0
to I/O3
DQMB /CS
D12
I/O0
to I/O3
DQMB /CS
D13
I/O0
to I/O3
DQMB /CS
D27
I/O0
to I/O3
DQMB /CS
D28
I/O0
to I/O3
DQMB /CS
D29
I/O0
to I/O3
DQMB /CS
D30
I/O0
to I/O3
DQMB /CS
D31
I/O0
to I/O3
DQMB /CS
D5
I/O0
to I/O3
DQMB /CS
D23
I/O0
to I/O3
RDQMB6
DQ48 to DQ51
4
10Ω
DQMB /CS
D14
I/O0
to I/O3
DQMB /CS
D32
I/O0
to I/O3
DQMB /CS
D6
I/O0
to I/O3
DQMB /CS
D24
I/O0
to I/O3
DQ52 to DQ55
4
10Ω
DQMB /CS
D15
I/O0
to I/O3
DQMB /CS
D33
I/O0
to I/O3
DQMB /CS
D7
I/O0
to I/O3
DQMB /CS
D25
I/O0
to I/O3
RDQMB7
DQ56 to DQ59
4
10Ω
DQMB /CS
D16
I/O0
to I/O3
DQMB /CS
D34
I/O0
to I/O3
DQMB /CS
D8
I/O0
to I/O3
DQMB /CS
D26
I/O0
to I/O3
DQ60 to DQ63
4
10Ω
DQMB /CS
D17
I/O0
to I/O3
DQMB /CS
D35
I/O0
to I/O3
CLK0
/RCS0, /RCS1, /RCS2, /RCS3
RDQMB0 to RDQMB7
RBA0 to RBA1 -> BA0 to BA1: SDRAMs D0 to D35 CLK1
RA0 to RA12 -> A0 to A12: SDRAMs D0 to D35 to CLK3
/RRAS -> /RAS: SDRAMs D0 to D35
10Ω
PLL
12pF
10Ω
12pF
VSS
CLK: SDRAMs
(D0 to D35)
Register
/RCAS -> /CAS: SDRAMs D0 to D35
RCKE0 -> CKE: SDRAMs D0 to D35
/RWE-> /WE: SDRAMs D0 to D35
Serial PD
VDD
0.0022µF × 21pcs
VSS
VDD (D0 to D35, U0)
0.22µF × 28pcs
VSS (D0 to D35, U0)
SCL
SCL
SDA
U0
WP
A0 A1 A2
SDA
* D0 to D35: 256M bits SDRAM TCP
PLL: 2510
Register: 162834
U0: 2k bits EEPROM
Notes:
SA0 SA1 SA2 VSS
1. The SDA pull-up resistor is required due to the open-drain/open-collector output.
2. The SCL pull-up resistor is recommended because of the normal SCL line inacitve "high" state.
Data Sheet E0106E30 (Ver. 3.0)
7
7페이지 | |||
구 성 | 총 15 페이지수 | ||
다운로드 | [ EBS11RC4ACNA-7A.PDF 데이터시트 ] |
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부품번호 | 상세설명 및 기능 | 제조사 |
EBS11RC4ACNA-75 | 1 GB Registered SDRAM DIMM | Elpida Memory |
EBS11RC4ACNA-7A | 1 GB Registered SDRAM DIMM | Elpida Memory |
DataSheet.kr | 2020 | 연락처 | 링크모음 | 검색 | 사이트맵 |