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EBS21RC2ACNA 데이터시트 PDF




Elpida Memory에서 제조한 전자 부품 EBS21RC2ACNA은 전자 산업 및 응용 분야에서
광범위하게 사용되는 반도체 소자입니다.


PDF 형식의 EBS21RC2ACNA 자료 제공

부품번호 EBS21RC2ACNA 기능
기능 2GB Registered SDRAM DIMM
제조업체 Elpida Memory
로고 Elpida Memory 로고


EBS21RC2ACNA 데이터시트 를 다운로드하여 반도체의 전기적 특성과 매개변수에 대해 알아보세요.



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EBS21RC2ACNA 데이터시트, 핀배열, 회로
DATA SHEET
2GB Registered SDRAM DIMM
EBS21RC2ACNA (256M words × 72 bits, 2 banks)
Description
Features
The EBS21RC2ACNA is 256M words × 72 bits, 2
banks Synchronous Dynamic RAM Registered Module,
mounted 72 pieces of 256M bits SDRAM sealed in
TCP package. This module provides high density and
large quantities of memory in a small space without
utilizing the surface mounting technology. Decoupling
capacitors are mounted on power supply line for noise
reduction.
Note: Do not push the cover or drop the modules in
order to protect from mechanical defects, which
would be electrical defects.
Fully compatible with 8 bytes DIMM: JEDEC
standard outline
168-pin socket type dual in line memory module
(DIMM)
PCB height: 41.91mm (1.65inch )
Lead pitch: 1.27mm
3.3V power supply
Clock frequency: 133MHz (max.)
LVTTL interface
Data bus width: × 72 ECC
Single pulsed /RAS
4 Banks can operates simultaneously and
independently
Burst read/write operation and burst read/single write
operation capability
Programmable burst length (BL): 1, 2, 4, 8
2 variations of burst sequence
Sequential
Interleave
Programmable /CAS latency (CL): 2, 3
Registered inputs with one clock delay
Byte control by DQMB
Refresh cycles: 8192 refresh cycles/64ms
2 variations of refresh
Auto refresh
Self refresh
1 piece of PLL clock driver, 3 pieces of register driver
and 1 piece of serial EEPROM (2k bits) for Presence
Detect (SPD) on PCB.
Document No. E0105E50 (Ver. 5.0)
Date Published June 2002 (K) Japan
URL: http://www.elpida.com
Elpida Memory, Inc. 2001-2002




EBS21RC2ACNA pdf, 반도체, 판매, 대치품
EBS21RC2ACNA
Serial PD Matrix*1
Byte No. Function described
0
Number of bytes used by module
manufacturer
1 Total SPD memory size
2 Memory type
3 Number of row addresses bits
4 Number of column addresses bits
5 Number of banks
6 Module data width
7 Module data width (continued)
8 Module interface signal levels
SDRAM cycle time
9 (highest /CAS latency)
7.5ns
SDRAM access from Clock
10 (highest /CAS latency)
5.4ns
11 Module configuration type
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Hex value
1 0 0 0 0 0 0 0 80H
0 0 0 0 1 0 0 0 08H
0 0 0 0 0 1 0 0 04H
0 0 0 0 1 1 0 1 0DH
0 0 0 0 1 1 0 0 0CH
0 0 0 0 0 0 1 0 02H
0 1 0 0 1 0 0 0 48H
0 0 0 0 0 0 0 0 00H
0 0 0 0 0 0 0 1 01H
0 1 1 1 0 1 0 1 75H
0 1 0 1 0 1 0 0 54H
0 0 0 0 0 0 1 0 02H
12 Refresh rate/type
1 0 0 0 0 0 1 0 82H
13 SDRAM width
0 0 0 0 0 0 1 0 02H
14 Error checking SDRAM width 0 0 0 0 0 0 1 0 02H
SDRAM device attributes:
15 minimum clock delay for back-to- 0 0 0 0 0 0 0 1 01H
back random column addresses
16
SDRAM device attributes:
Burst lengths supported
0 0 0 0 1 1 1 1 0FH
17
SDRAM device attributes: number of
banks on SDRAM device
0
0
0
0
0
1
0
0
04H
18
SDRAM device attributes:
/CAS latency
0 0 0 0 0 1 1 0 06H
19
SDRAM device attributes:
/CS latency
0 0 0 0 0 0 0 1 01H
20
SDRAM device attributes:
/WE latency
0 0 0 0 0 0 0 1 01H
21 SDRAM device attributes
0 0 0 1 1 1 1 1 1FH
22 SDRAM device attributes: General 0 0 0 0 1 1 1 0 0EH
SDRAM cycle time
23 (2nd highest /CAS latency)
(-7A) 7.5ns
0 1 1 1 0 1 0 1 75H
(-75) 10ns
1 0 1 0 0 0 0 0 A0H
SDRAM access from Clock
24 (2nd highest /CAS latency)
(-7A)5.4ns
0 1 0 1 0 1 0 0 54H
(-75) 6ns
0 1 1 0 0 0 0 0 60H
SDRAM cycle time
25 (3rd highest /CAS latency)
Undefined
0 0 0 0 0 0 0 0 00H
SDRAM access from Clock (3rd
26 highest /CAS latency)
0 0 0 0 0 0 0 0 00H
Undefined
Comments
128
256 byte
SDRAM
13
12
2
72 bit
0 (+)
LVTTL
CL = 3*5
ECC
Normal
(7.8125 µs)
Self refresh
128M × 2
×2
1 CLK
1, 2, 4, 8
4
2, 3
0
0
Registered
VDD ± 10%
CL = 2*5
Data Sheet E0105E50 (Ver. 5.0)
4

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EBS21RC2ACNA 전자부품, 판매, 대치품
EBS21RC2ACNA
Block Diagram
/RCS0
/RCS1
RDQMB0
4 10
DQ0 to DQ3
4 10
DQ4 to DQ7
RDQMB1
4 10
DQ8 to DQ11
4 10
DQ12 to DQ15
4 10
CB0 to CB3
DQMB /CS
D0/D1
I/O0, I/O1
DQMB /CS
D2/D3
I/O0, I/O1
DQMB /CS
D4/D5
I/O0, I/O1
DQMB /CS
D6/D7
I/O0, I/O1
DQMB /CS
D8/D9
I/O0, I/O1
DQMB /CS
D36/D37
I/O0, I/O1
DQMB /CS
D38/D39
I/O0, I/O1
DQMB /CS
D40/D41
I/O0, I/O1
DQMB /CS
D42/D43
I/O0, I/O1
DQMB /CS
D44/D45
I/O0, I/O1
RDQMB4
4 10
DQ32 to DQ35
4 10
DQ36 to DQ39
RDQMB5
4 10
DQ40 to DQ43
4 10
DQ44 to DQ47
4 10
CB4 to CB7
DQMB /CS
D18/D19
I/O0, I/O1
DQMB /CS
D20/D21
I/O0, I/O1
DQMB /CS
D22/D23
I/O0, I/O1
DQMB /CS
D24/D25
I/O0, I/O1
DQMB /CS
D26/D27
I/O0, I/O1
DQMB /CS
D54/D55
I/O0, I/O1
DQMB /CS
D56/D57
I/O0, I/O1
DQMB /CS
D58/D59
I/O0, I/O1
DQMB /CS
D60/D61
I/O0, I/O1
DQMB /CS
D62/D63
I/O0, I/O1
/RCS2
/RCS3
RDQMB2
4 10
DQ16 to DQ19
4 10
DQ20 to DQ23
RDQMB3
4 10
DQ24 to DQ27
4 10
DQ28 to DQ31
DQMB /CS
D10/D11
I/O0, I/O1
DQMB /CS
D12/D13
I/O0, I/O1
DQMB /CS
D14/D15
I/O0, I/O1
DQMB /CS
D16/D17
I/O0, I/O1
DQMB /CS
D46/D47
I/O0, I/O1
DQMB /CS
D48/D49
I/O0, I/O1
DQMB /CS
D50/D51
I/O0, I/O1
DQMB /CS
D52/D53
I/O0, I/O1
RDQMB6
4 10
DQ48 to DQ51
4 10
DQ52 to DQ55
RDQMB7
4 10
DQ56 to DQ59
4 10
DQ60 to DQ63
DQMB /CS
D28/D29
I/O0, I/O1
DQMB /CS
D30/D31
I/O0, I/O1
DQMB /CS
D32/D33
I/O0, I/O1
DQMB /CS
D34/D35
I/O0, I/O1
DQMB /CS
D64/D65
I/O0, I/O1
DQMB /CS
D66/D67
I/O0, I/O1
DQMB /CS
D68/D69
I/O0, I/O1
DQMB /CS
D70/D71
I/O0, I/O1
/CS0, /CS1, /CS2, /CS3
DQMB0 to DQMB7
BA0 to BA1
A0 to A12
/RAS
/CAS
CKE0
/WE
VDD
REGE
PLL CLK
10k
R
E
G
I
S
T
E
R
CLK0
/RCS0, /RCS1, /RCS2, /RCS3
RDQMB0 to RDQMB7
RBA0 to RBA1 -> BA0 to BA1: SDRAMs D0 to D71 CLK1
RA0 to RA12 -> A0 to A12: SDRAMs D0 to D71 to CLK3
/RRAS -> /RAS: SDRAMs D0 to D71
/RCAS -> /CAS: SDRAMs D0 to D71
RCKE0 -> CKE: SDRAMs D0 to D71
/RWE -> /WE: SDRAMs D0 to D71
VDD
0.0022µF × 41 pcs
Serial PD
VSS
10
PLL
12pF
10
12pF
VSS
CLK : SDRAMs
(D0 to D71)
Register
VDD (D0 to D71, U0)
0.22µF × 32 pcs
VSS (D0 to D71, U0)
SCL
SCL
SDA
U0
WP
A0 A1 A2
SDA
* D0 to D71: 256M bits SDRAM TCP
PLL: 2510
Register: 162834
U0: 2k bits EEPROM
Notes:
SA0 SA1 SA2 VSS
1. The SDA pull-up resistor is required due to the open-drain/open-collector output.
2. The SCL pull-up resistor is recommended because of the normal SCL line inacitve "high" state.
Data Sheet E0105E50 (Ver. 5.0)
7

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