EBS25UC8APMA-80 Datasheet PDF - Elpida Memory
| Part Number | EBS25UC8APMA-80 | |
| Description | 256MB SDRAM Micro DIMM | |
| Manufacturers | Elpida Memory | |
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DATA SHEET
256MB SDRAM Micro DIMM
EBS25UC8APMA (32M words × 64 bits, 1 bank)
Description
The EBS25UC8APMA is 32M words × 64 bits, 1 bank
Synchronous Dynamic RAM Micro Dual In-line Memory
Module (Micro DIMM), mounted 8 pieces of 256M bits
SDRAM sealed in µBGA package. This module
provides high density and large quantities of memory in
a small space without utilizing the surface mounting
technology. Decoupling capacitors are mounted on
power supply line for noise reduction.
Note : Do not push the cover or drop the modules in
order to protect from mechanical defects, which
would be electrical defects.
Features
• Fully compatible with 8 bytes Micro DIMM: JEDEC
standard outline
• 144-pin socket type micro dual in line memory
module (Micro DIMM)
PCB height: 30.00mm (1.18inch )
Lead pitch: 0.50mm
• 3.3V power supply
• Clock frequency: 100MHz/133MHz (max.)
• LVTTL interface
• Data bus width: × 64 non-ECC
• Single pulsed /RAS
• 4 Banks can operates simultaneously and
independently
• Burst read/write operation and burst read/single write
operation capability
• Programmable burst length (BL): 1, 2, 4, 8, Full page
• 2 variations of burst sequence
Sequential
Interleave
• Programmable /CAS latency (CL): 2, 3
• Byte control by DQMB
• Refresh cycles: 8192 refresh cycles/64ms
• 2 variations of refresh
Auto refresh
Self refresh
Document No. E0241E30 (Ver. 3.0)
Date Published May 2002 (K) Japan
URL: http://www.elpida.com
Elpida Memory, Inc. 2002
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EBS25UC8APMA
Byte No. Function described
28
Row active to row active min
(-7A/7AL, -75/75L)
(-80/80L)
29
/RAS to /CAS delay min
(-7A/7AL)
(-75/75L, -80/80L)
30
Minimum /RAS pulse width
(-7A/7AL, -75/75L)
(-80/80L)
31 Density of each bank on module
Address and command signal input
32 setup time
(-7A/7AL, -75/75L)
(-80/80L)
Address and command signal input
33 hold time
(-7A/7AL, -75/75L)
(-80/80L)
34
Data signal input setup time
(-7A/7AL, -75/75L)
(-80/80L)
35
Data signal input hold time
(-7A/7AL, -75/75L)
(-80/80L)
36 to 61 Superset information
62 SPD data revision code
63
Checksum for Bytes 0 to 62
(-7A/7AL)
(-75/75L)
(-80/80L)
64 to 65 Manufacturer’s JEDEC ID code
66 Manufacturer’s JEDEC ID code
67 to 71 Manufacturer’s JEDEC ID code
72 Manufacturing location
73 to 90 Manufacturer’s part number
91 to 92 Revision code
93 to 94 Manufacturing date
95 to 98 Assembly serial number
99 to 127 Manufacturer specific data
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Hex value
0 0 0 0 1 1 1 1 0FH
0 0 0 1 0 0 0 0 10H
0 0 0 0 1 1 1 1 0FH
0 0 0 1 0 1 0 0 14H
0 0 1 0 1 1 0 1 2DH
0 0 1 1 0 0 0 0 30H
0 1 0 0 0 0 0 0 40H
0 0 0 1 0 1 0 1 15H
0 0 1 0 0 0 0 0 20H
0 0 0 0 1 0 0 0 08H
0 0 0 1 0 0 0 0 10H
0 0 0 1 0 1 0 1 15H
0 0 1 0 0 0 0 0 20H
0 0 0 0 1 0 0 0 08H
0 0 0 1 0 0 0 0 10H
0 0 0 0 0 0 0 0 00H
0 0 0 1 0 0 1 0 12H
0 1 1 1 1 0 0 0 78H
1 0 1 1 1 0 0 1 B9H
1 1 1 1 1 0 1 0 FAH
0 1 1 1 1 1 1 1 7FH
1 1 1 1 1 1 1 0 FEH
0 0 0 0 0 0 0 0 00H
Comments
15ns
16ns
15ns
20ns
45ns
48ns
256MB
1.5ns
2ns
0.8ns
1ns
1.5ns
2ns
0.8ns
1ns
1.2
Continuation code
Elpida Memory
Data Sheet E0241E30 (Ver. 3.0)
5
Preview 5 Page |
Part DetailsOn this page, you can learn information such as the schematic, equivalent, pinout, replacement, circuit, and manual for EBS25UC8APMA-80 electronic component. |
| Information | Total 14 Pages | |
| Link URL | [ Copy URL to Clipboard ] | |
| Download | [ EBS25UC8APMA-80.PDF Datasheet ] | |
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