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EBS52UC8APSA-7AL 데이터시트 PDF




Elpida Memory에서 제조한 전자 부품 EBS52UC8APSA-7AL은 전자 산업 및 응용 분야에서
광범위하게 사용되는 반도체 소자입니다.


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부품번호 EBS52UC8APSA-7AL 기능
기능 512MB SDRAM S.O.DIMM
제조업체 Elpida Memory
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EBS52UC8APSA-7AL 데이터시트, 핀배열, 회로
DATA SHEET
512MB SDRAM S.O.DIMM
EBS52UC8APSA (64M words × 64 bits, 2 bank)
Description
The EBS52UC8APSA is 64M words × 64 bits, 2 banks
Synchronous Dynamic RAM Small Outline Dual In-line
Memory Module (S.O.DIMM), mounted 16 pieces of
256M bits SDRAM sealed in µBGApackage. This
module provides high density and large quantities of
memory in a small space without utilizing the surface
mounting technology. Decoupling capacitors are
mounted on power supply line for noise reduction.
Note : Do not push the cover or drop the modules in
order to protect from mechanical defects, which
would be electrical defects.
Features
Fully compatible with 8 bytes S.O.DIMM: JEDEC
standard outline
144-pin socket type small outline dual in line memory
module (S.O.DIMM)
PCB height: 31.75mm (1.25inch )
Lead pitch: 0.80mm
3.3V power supply
Clock frequency: 133MHz (max.)
LVTTL interface
Data bus width: × 64 non-ECC
Single pulsed /RAS
4 Banks can operates simultaneously and
independently
Burst read/write operation and burst read/single write
operation capability
Programmable burst length (BL): 1, 2, 4, 8, Full page
2 variations of burst sequence
Sequential
Interleave
Programmable /CAS latency (CL): 2, 3
Byte control by DQMB
Refresh cycles: 8192 refresh cycles/64ms
2 variations of refresh
Auto refresh
Self refresh
Document No. E0240E20 (Ver. 2.0)
Date Published May 2002 (K) Japan
URL: http://www.elpida.com
Elpida Memory, Inc. 2001-2002




EBS52UC8APSA-7AL pdf, 반도체, 판매, 대치품
EBS52UC8APSA
Serial PD Matrix
Byte No.
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25 to 26
27
Function described
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Hex value
Number of bytes used by module
manufacturer
1
0
0
0
0
0
0
0
80H
Total SPD memory size
0 0 0 0 1 0 0 0 08H
Memory type
0 0 0 0 0 1 0 0 04H
Number of row addresses bits
0 0 0 0 1 1 0 1 0DH
Number of column addresses bits 0 0 0 0 1 0 1 0 0AH
Number of banks
0 0 0 0 0 0 1 0 02H
Module data width
0 1 0 0 0 0 0 0 40H
Module data width (continued)
0 0 0 0 0 0 0 0 00H
Module interface signal levels
0 0 0 0 0 0 0 1 01H
SDRAM cycle time at CL = 3
(highest /CAS latency)
0 1 1 1 0 1 0 1 75H
SDRAM
(highest
access from Clock
/CAS latency)
at
CL
=
3
0
1
0
1
0
1
0
0
54H
Module configuration type
0 0 0 0 0 0 0 0 00H
Refresh rate/type
1 0 0 0 0 0 1 0 82H
SDRAM width
0 0 0 0 1 0 0 0 08H
Error checking SDRAM width
0 0 0 0 0 0 0 0 00H
SDRAM device attributes:
minimum clock delay for back-to- 0 0 0 0 0 0 0 1 01H
back random column addresses
SDRAM device attributes:
Burst lengths supported
1 0 0 0 1 1 1 1 8FH
SDRAM device attributes: number of
banks on SDRAM device
0
0
0
0
0
1
0
0
04H
SDRAM device attributes:
/CAS latency
SDRAM device attributes:
/CS latency
0 0 0 0 0 1 1 0 06H
0 0 0 0 0 0 0 1 01H
SDRAM device attributes:
/WE latency
0 0 0 0 0 0 0 1 01H
SDRAM device attributes
0 0 0 0 0 0 0 0 00H
SDRAM device attributes: General 0 0 0 0 1 1 1 0 0EH
SDRAM cycle time at CL = 2
(2nd highest /CAS latency)
(-7A/7AL)
0 1 1 1 0 1 0 1 75H
(-75/75L)
1 0 1 0 0 0 0 0 A0H
SDRAM access from Clock at CL = 2
(2nd highest /CAS latency)
0 1 0 1 0 1 0 0 54H
(-7A/7AL)
(-75/75L)
0 1 1 0 0 0 0 0 60H
0 0 0 0 0 0 0 0 00H
Minimum row precharge time
(-7A/7AL)
(-75/75L)
0 0 0 0 1 1 1 1 0FH
0 0 0 1 0 1 0 0 14H
Comments
128 bytes
256 bytes
SDRAM
13
10
2
64
0
LVTTL
7.5ns
5.4ns
None.
7.8µs
×8
None.
1 CLK
1,2,4,8,F
4
2,3
0
0
7.5ns
10ns
5.4ns
6ns
15ns
20ns
Data Sheet E0240E20 (Ver. 2.0)
4

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EBS52UC8APSA-7AL 전자부품, 판매, 대치품
EBS52UC8APSA
Electrical Specifications
All voltages are referenced to VSS (GND).
After power up, wait more than 100 µs and then, execute power on sequence and CBR (Auto) refresh before
proper device operation is achieved.
Absolute Maximum Ratings
Parameter
Symbol
Value
Unit Note
Voltage on any pin relative to VSS
Supply voltage relative to VSS
VT
VDD
–0.5 to VDD + 0.5
(4.6 (max.))
–0.5 to +4.6
V
V
Short circuit output current
IOS 50
mA
Power dissipation
PD 16
W
Operating temperature
TA 0 to +70
°C 1
Storage temperature
Tstg
–55 to +125
°C
Notes: 1. SDRAM device specification
Caution
Exposing the device to stress above those listed in Absolute Maximum Ratings could cause
permanent damage. The device is not meant to be operated under conditions outside the limits
described in the operational section of this specification Exposure to Absolute Maximum Rating
conditions for extended periods may affect device reliability.
DC Operating Conditions (TA = 0 to +70°C) (SDRAM device specification)
Parameter
Symbol
min. max.
Supply voltage
VDD
3.0 3.6
VSS
00
Input high voltage
VIH 2.0 VDD + 0.3
Input low voltage
VIL 0.3 0.8
Notes: 1. The supply voltage with all VDD pins must be on the same level.
2. The supply voltage with all VSS pins must be on the same level.
3. VIH (max.) = VDD + 2.0V for pulse width 3ns at VDD.
4. VIL (min.) = VSS 2.0V for pulse width 3ns at VSS.
Unit
V
V
V
V
Note
1
2
3
4
Data Sheet E0240E20 (Ver. 2.0)
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