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DM7497 데이터시트 PDF




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부품번호 DM7497 기능
기능 Synchronous Modulo-64 Bit Rate Multiplier
제조업체 National Semiconductor
로고 National Semiconductor 로고


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DM7497 데이터시트, 핀배열, 회로
5497 DM7497
Synchronous Modulo-64 Bit Rate Multiplier
General Description
The ’97 contains a synchronous 6-stage binary counter and
six decoding gates that serve to gate the clock through to
the output at a sub-multiple of the input frequency The out-
put pulse rate relative to the clock frequency is determined
by signals applied to the Select (S0–S5) inputs Both true
and complement outputs are available along with an enable
input for each A Count Enable input and a Terminal Count
output are provided for cascading two or more packages
An asynchronous Master Reset input prevents counting and
resets the counter
Connection Diagram
Logic Symbol
Dual-In-Line Package
June 1989
TL F 9780 – 1
Order Number 5497DMQB 5497FMQB or DM7497N
See NS Package Number J16A N16E or W16A
VCC e Pin 16
GND e Pin 8
Pin Names
S0 – S5
EZ
EY
CE
CP
MR
OZ
Oy
TC
Description
Rate Select Inputs
OZ Enable Input (Active LOW)
OY Enable Input
Count Enable Input (Active LOW)
Clock Pulse Input (Active Rising Edge)
Asynchronous Master Reset Input (Active HIGH)
Gated Clock Output (Active LOW)
Complement Output (Active HIGH)
Terminal Count Output (Active LOW)
TL F 9780 – 2
C1995 National Semiconductor Corporation TL F 9780
RRD-B30M115 Printed in U S A




DM7497 pdf, 반도체, 판매, 대치품
Functional Description
The ’97 contains six JK flip-flops connected as a synchro-
nous modulo-64 binary counter A LOW signal on the Count
Enable (CE) input permits counting with all state changes
initiated simultaneously by the rising edge of the clock
When the count reaches maximum (63) with all Qs HIGH
the Terminal Count (TC) output will be LOW if CE is LOW A
HIGH signal on Master Reset (MR) resets the flip-flops and
prevents counting although output pulses can still occur if
the clock is running EZ is LOW and S5 is HIGH
The flip-flop outputs are decoded by a 6-wide AND-OR-IN-
VERT gate Each AND gate also contains the buffered and
inverted CP and Z-enable (EZ) functions as well as one of
the Select (S0 – S5) inputs The Z output OZ is normally
HIGH and goes LOW when CP and EZ are LOW and any of
the AND gates has its other inputs HIGH The AND gates
are enabled by the counter at different times and different
rates relative to the clock For example the gate to which
S5 is connected is enabled during every other clock period
assuming S5 is HIGH Thus during one complete cycle of
the counter (64 clocks) the S5 gate is enabled 32 times and
can therefore gate 32 clocks per cycle to the output The S4
gate is enabled 16 times per cycle the S3 gate 8 times per
cycle etc The output pulse rate thus depends on the clock
rate and which of the S0–S5 inputs is HIGH
fout
e
m
64

fin
Where m e S5  25 a S4  24 a S3  23 a S2  22 a S1
 21 a S0  20
Thus by appropriate choice of signals applied to the S0–S5
inputs the output pulse rate can range from to of
the clock rate as suggested in Rate Select Table There is
no output pulse when the counter is in the ‘‘all ones’’ condi-
tion When m is 1 2 4 8 16 or 32 the output pulses are
evenly spaced assuming that the clock frequency is con-
stant For any other value of m the output pulses are not
evenly spaced since the pulse train is formed by interleav-
ing pulses passed by two or more of the AND gates The
Pulse Pattern Table indicates the output pattern for several
values of m In each row a one means that the OZ output
will be HIGH during that entire clock period while a zero
means that OZ will be LOW when the clock is LOW in that
period The first column in the output field coincides with the
‘‘all zeroes’’ condition of the counter while the last column
represents the ‘‘all ones’’ condition The pulse pattern for
any particular value of m can be deduced by factoring it into
the sum of appropriate powers of two (e g 19 e 16 a 2 a
1) and combining the pulses (i e the zeroes) shown for
each for the relevant powers of two (e g for m e 16 2 and
1)
The Y output OY is the complement of OZ and is thus nor-
mally LOW A LOW signal on the Y-enable input EY dis-
ables Oy To expand the multiplier to 12-bit rate select two
packages can be cascaded as shown in Figure A Both cir-
cuits operate from the basic clock with the TC output of the
first acting to enable both counting and the output pulses of
the second package Thus the second counter advances at
only the rate of the first and a full cycle of the two coun-
ters combined requires 4096 clocks Each rate select input
of the first package has 64 times the weight of its counter-
part in the second package
fout
e
m1 a m2
64  64

fin
Where m1 e S5  211 a S4  210 a S3  29 a S2  28 a
S1  27 a S0  26 (first package)
m2 e S5  25 a S4  24 a S3  23 a S2  22 a
S1  21 a S0  20 (second package)
Combined output pulses are obtained in Figure A by letting
the Z output of the first circuit act as the Y-enable function
for the second with the interleaved pulses obtained from
the Y output of the second package being opposite in phase
to the clock
FIGURE A Cascading for 12-Bit Rate Select
TL F 9780 – 3
4

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DM7497 전자부품, 판매, 대치품
Physical Dimensions inches (millimeters)
16-Lead Ceramic Dual-In-Line Package (J)
Order Number 5497DMQB
NS Package Number J16A
16-Lead Molded Dual-In-Line Package (N)
Order Number DM7497N
NS Package Number N16E
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