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부품번호 | DM74ALS109A 기능 |
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기능 | Dual J-K Positive-Edge-Triggered Flip-Flop | ||
제조업체 | Fairchild Semiconductor | ||
로고 | |||
전체 6 페이지수
April 1984
Revised February 2000
DM74ALS109A
Dual J-K Positive-Edge-Triggered Flip-Flop
with Preset and Clear
General Description
The DM74ALS109A is a dual edge-triggered flip-flop. Each
flip-flop has individual J, K, clock, clear and preset inputs,
and also complementary Q and Q outputs.
Information at input J or K is transferred to the Q output on
the positive going edge of the clock pulse. Clock triggering
occurs at a voltage level of the clock pulse and is not
directly related to the transition time of the positive going
pulse. When the clock input is at either the HIGH or LOW
level, the J, K input signal has no effect.
Asynchronous preset and clear inputs will set or clear Q
output respectively upon the application of low level signal.
The J-K design allows operation as a D flip-flop by tying the
J and K inputs together.
Features
s Switching specifications at 50 pF
s Switching specifications guaranteed over full tempera-
ture and VCC range
s Advanced oxide-isolated, ion-implanted Schottky TTL
process
s Functionally and pin for pin compatible with Schottky
and LS TTL counterpart
s Improved AC performance over LS109 at approximately
half the power
Ordering Code:
Order Number Package Number
Package Description
DM74ALS109AM
M16A
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow
DM74ALS109AN
N16E
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagram
Function Table
Inputs
Outputs
PR CLR CK J K
Q
Q
LHXXX
H
L
HL XXX
L
H
L L X X X H (Note 1) H (Note 1)
HH ↑ L L
L
H
HH ↑HL
TOGGLE
HH ↑ LH
HH ↑HH
Q0
H
Q0
L
HH L XX
Q0
Q0
L = LOW State
H = HIGH State
X = Don't Care
↑ = Positive Edge Transition,
Q0 = Previous Condition of Q
Note 1: This condition is nonstable; it will not persist when present and
clear inputs return to their inactive (HIGH) level. The output levels in this
condition are not guaranteed to meet the VOH specification.
© 2000 Fairchild Semiconductor Corporation DS006196
www.fairchildsemi.com
Electrical Characteristics
over recommended operating free-air temperature range. All typical values are measured at VCC = 5V, TA = 25°C.
Symbol
Parameter
Conditions
Min Typ
Max
Units
VIK Input Clamp Voltage
VOH HIGH Level
Output Voltage
VOL LOW Level
Output Voltage
VCC = 4.5V, II = −18 mA
IOH = −400 µA
VCC = 4.5V to 5.5V
VCC = 4.5V
VIH = 2V
IOL = 4 mA
IOL = 8 mA
VCC − 2
0.25
0.35
−1.5
0.4
0.5
V
V
V
V
II Input Current at Max
Input Voltage
VCC = 5.5V,
VIH = 7V
Clock, J, K
Preset, Clear
0.1
mA
0.2
IIH High Level
Input Current
VCC = 5.5V,
VIH = 2.7V
Clock, J, K
Preset, Clear
20
µA
40
IIL Low Level
VCC = 5.5V,
Clock, J, K
−0.2
Input Current
VIL = 0.4V
Preset, Clear
−0.4
IO (Note 4) Output Drive Current
VCC = 5.5V, VO = 2.25V
−30 −112
ICC Supply Current
VCC = 5.5V (Note 5)
2.4 4
Note 4: The output conditions have been chosen to produce a current that closely approximates one half of the true short circuit output current, IOS.
Note 5: ICC is measured with J, K, CLK and PRESET grounded, then with J, K, CLK and CLEAR grounded.
mA
mA
mA
Switching Characteristics
over recommended operating free air temperature range
Symbol
Parameter
Conditions
fMAX
tPLH
tPHL
Maximum Clock Frequency
Propagation Delay Time
LOW-to-HIGH Level Output
Propagation Delay Time
HIGH-to-LOW Level Output
VCC = 4.5V to 5.5V
RL = 500Ω
CL = 50 pF
tPLH Propagation Delay Time
LOW-to-HIGH Level Output
tPHL Propagation Delay Time
HIGH-to-LOW Level Output
From
To
Preset or Clear Q or Q
Preset or Clear Q or Q
Clock
Q or Q
Clock
Q or Q
Min
Max
Units
34 MHz
3 13 ns
5 15 ns
5 16 ns
5 18 ns
www.fairchildsemi.com
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부품번호 | 상세설명 및 기능 | 제조사 |
DM74ALS109A | Dual J-K Positive-Edge-Triggered Flip-Flop | Fairchild Semiconductor |
DataSheet.kr | 2020 | 연락처 | 링크모음 | 검색 | 사이트맵 |