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DM74AS169AN 데이터시트 PDF




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부품번호 DM74AS169AN 기능
기능 Synchronous 4-Bit Binary Up/Down Counter
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DM74AS169AN 데이터시트, 핀배열, 회로
April 1984
Revised March 2000
DM74AS169A
Synchronous 4-Bit Binary Up/Down Counter
General Description
These synchronous presettable counters feature an inter-
nal carry look ahead for cascading in high speed counting
applications. The DM74AS169 is a 4-bit binary up/down
counter. The carry output is decoded to prevent spikes dur-
ing normal mode of counting operation. Synchronous oper-
ation is provided so that outputs change coincident with
each other when so instructed by count enable inputs and
internal gating. This mode of operation eliminates the out-
put counting spikes which are normally associated with
asynchronous (ripple clock) counters. A buffered clock
input triggers the four flip-flops on the rising (positive going)
edge of clock input waveform.
These counters are fully programmable; that is, the outputs
may each be preset either HIGH or LOW. The load input
circuitry allows loading with carry-enable output of cas-
caded counters. As loading is synchronous, setting up a
LOW level at the load input disables the counter and
causes the outputs to agree with the data inputs after the
next clock pulse.
The carry look-ahead circuitry permits cascading counters
for n-bit synchronous applications without additional gating.
Both count enable inputs (P and T) must be LOW to count.
The direction of the count is determined by the level of the
up/down input. When the input is HIGH, the counter counts
UP; when LOW, it counts DOWN. Input T is fed forward to
enable the carry outputs. The carry output thus enabled will
produce a LOW level output pulse with a duration approxi-
mately equal to the HIGH portion of the QA output when
counting UP, and approximately equal to the LOW portion
of the QA output when counting DOWN. This LOW level
overflow carry pulse can be used to enable successively
cascaded stages. Transitions at the enable P or T inputs
are allowed regardless of the level of the clock input.
The control functions for these counters are fully synchro-
nous. Changes at control inputs (enable P, enable T, load,
up/down) which modify the operating mode have no effect
until clocking occurs. The function of the counter (whether
enabled, disabled, loading or counting) will be dictated
solely by the conditions meeting the stable setup and hold
times.
Features
s Switching Specifications at 50 pF
s Switching Specifications guaranteed over full tempera-
ture and VCC range
s Advanced oxide-isolated, ion-implanted Schottky TTL
process
s Functionally and pin-for-pin compatible with Schottky
and low power Schottky TTL counterpart
s Improved AC performance over Schottky and low power
Schottky counterparts
s Synchronously programmable
s Internal look ahead for fast counting
s Carry output for n-bit cascading
s Synchronous counting
s Load control line
s ESD inputs
Ordering Code:
Order Number Package Number
Package Description
DM74AS169AM
M16A
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow
DM74AS169AN
N16E
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
© 2000 Fairchild Semiconductor Corporation DS006292
www.fairchildsemi.com




DM74AS169AN pdf, 반도체, 판매, 대치품
Switching Characteristics
over recommended operating free air temperature range
Symbol
Parameter
Conditions
From
To
Min
Max
Units
fMAX
tPLH
tPHL
tPLH
tPHL
Maximum Clock Frequency
Propagation Delay Time
LOW-to-HIGH Level Output
Propagation Delay Time
HIGH-to-LOW Level Output
Propagation Delay Time
LOW-to-HIGH Level Output
Propagation Delay Time
HIGH-to-LOW Level Output
VCC = 4.5V to 5.5V
RL = 500
CL = 50 pF
Clock
RIPPLE Carry
75
3
Clock
RIPPLE Carry
2
Clock
Any Q
1
Clock
Any Q
2
16.5
13
7
13
MHz
ns
ns
ns
ns
tPLH Propagation Delay Time
LOW-to-HIGH Level Output
En T
RIPPLE Carry 1.5
9
ns
tPHL Propagation Delay Time
HIGH-to-LOW Level Output
En T
RIPPLE Carry 1.5
9
ns
tPLH Propagation Delay Time
LOW-to-HIGH Level Output
U/D
(Note 3)
RIPPLE Carry
2
12 ns
tPHL Propagation Delay Time
HIGH-to-LOW Level Output
U/D
(Note 3)
RIPPLE Carry
2
13 ns
Note 3: Propagation delay time from up/down to ripple carry must be measured with the counter at either a minimum or a maximum count. As the logic level
of the up/down input is changed, the ripple carry output will follow. If the count is minimum (0), the ripple carry output transition will be in phase. If the count is
maximum, the ripple carry output will be out of phase.
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관련 데이터시트

부품번호상세설명 및 기능제조사
DM74AS169A

Synchronous 4-Bit Binary Up/Down Counter

Fairchild Semiconductor
Fairchild Semiconductor
DM74AS169AM

Synchronous 4-Bit Binary Up/Down Counter

Fairchild Semiconductor
Fairchild Semiconductor

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