DM74AS240WM Datasheet PDF - Fairchild Semiconductor
| Part Number | DM74AS240WM | |
| Description | 3-STATE Bus Driver/Receiver | |
| Manufacturers | Fairchild Semiconductor | |
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October 1986
Revised March 2000
DM74AS240 • DM74AS244
3-STATE Bus Driver/Receiver
General Description
This family of Advance Schottky 3-STATE Bus circuits are
designed to provide either bidirectional or unidirectional
buffer interface in Memory, Microprocessor, and Communi-
cation Systems. The output characteristics of the circuits
have low impedance sufficient to drive terminated trans-
mission lines down to 133Ω. The input characteristics of
the circuits likewise have a high impedance so it will not
significantly load the transmission line. The package con-
tains eight 3-STATE buffers organized with four buffers
having a common 3-STATE enable gate. The DM74AS240
and DM74AS244 are eight wide in a 20 pin package, and
may be used as a 4 wide bidirectional or eight wide unidi-
rectional. The buffer selection includes inverting and non-
inverting, with enable or disable 3-STATE control.
Features
s Advanced oxide-isolated, ion-implanted Schottky TTL
process
s Improved switching performance with less power dissi-
pation compared with Schottky counterpart
s Functional and pin compatible with 74LS and Schottky
counterpart
s Switching response specified into 500Ω and 50 pF
s Specified to interface with CMOS at VOH = VCC − 2V
Ordering Code:
Order Number Package Number
Package Description
DM74AS240WM
M20B
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
DM74AS240N
N20A
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
DM74AS244WM
M20B
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
DM74AS244N
N20A
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagrams
DM74AS240
DM74AS244
Function Tables
DM74AS240
Inputs
GA
LL
LH
HX
L = LOW Logic Level
Output
Y
H
L
Z
H = HIGH Logic Level
DM74AS244
Inputs
Output
GA
LL
LH
HX
Y
L
H
Z
X = Either LOW or HIGH Logic Level Z = High Impedance
© 2000 Fairchild Semiconductor Corporation DS006298
www.fairchildsemi.com
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Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Package Number N20A
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
www.fairchildsemi.com
5 www.fairchildsemi.com
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| Link URL | [ Copy URL to Clipboard ] | |
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