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부품번호 | DM74AS373 기능 |
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기능 | DM74AS373 | ||
제조업체 | Fairchild Semiconductor | ||
로고 | |||
전체 6 페이지수
April 1984
Revised March 2000
DM74AS373
Octal D-Type Transparent Latch with 3-STATE Outputs
General Description
These 8-bit registers feature totem-pole 3-STATE outputs
designed specifically for driving highly-capacitive or rela-
tively low-impedance loads. The high-impedance state and
increased high-logic-level drive provide these registers with
the capability of being connected directly to and driving the
bus lines in a bus-organized system without need for inter-
face or pull-up components. They are particularly attractive
for implementing buffer registers, I/O ports, bidirectional
bus drivers, and working registers.
The eight latches of the DM74AS373 are transparent D-
type latches, meaning that while the enable (G) is HIGH
the Q outputs will follow the data (D) inputs. When the
enable is taken LOW the output will be latched at the level
of the data that was set up.
A buffered output control input can be used to place the
eight outputs in either a normal logic state (HIGH or LOW
logic levels) or a high impedance state. In the high-imped-
ance state the outputs neither load nor drive the bus lines
significantly.
The output control does not affect the internal operation of
the latches. That is, the old data can be retained or new
data can be entered even while the outputs are OFF.
Features
s Switching specifications at 50 pF
s Switching specifications guaranteed over full tempera-
ture and VCC range
s Advanced oxide-isolated, ion-implanted Schottky TTL
process
s Functionally and pin for pin compatible with LS and ALS
TTL counterparts
s Improved AC performance over LS and ALS TTL coun-
terparts
s 3-STATE buffer-type outputs drive bus lines directly
Ordering Code:
Order Number Package Number
Package Description
DM74AS373WM
M20B
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
DM74AS373N
N20A
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagram
© 2000 Fairchild Semiconductor Corporation DS006309
www.fairchildsemi.com
Switching Characteristics
over recommended operating free air temperature range
Symbol
Parameter
Conditions
tPLH Propagation Delay Time
LOW-to-HIGH Level Output
tPHL Propagation Delay Time
HIGH-to-LOW Level Output
tPLH Propagation Delay Time
LOW-to-HIGH Level Output
tPHL Propagation Delay Time
HIGH-to-LOW Level Output
tPZH Output Enable Time
to HIGH Level Output
tPZL Output Enable Time
to LOW Level Output
tPHZ
Output Disable Time
from HIGH Level Output
tPLZ Output Disable Time
from LOW Level Output
VCC = 4.5V to 5.5V
RL = 500Ω
CL = 50 pF
From
Data
Data
Enable
Enable
Output
Control
Output
Control
Output
Control
Output
Control
To
Any Q
Any Q
Any Q
Any Q
Any Q
Any Q
Any Q
Any Q
Min Max
3.5 6
3.5 6
6.5 11.5
5 7.5
2 6.5
4.5 9.5
3 6.5
37
Units
ns
ns
ns
ns
ns
ns
ns
ns
www.fairchildsemi.com
4
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다운로드 | [ DM74AS373.PDF 데이터시트 ] |
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부품번호 | 상세설명 및 기능 | 제조사 |
DM74AS373 | Octal D-Type Transparent Latch with 3-STATE Outputs | Fairchild Semiconductor |
DM74AS373 | DM74AS373 | Fairchild Semiconductor |
DataSheet.kr | 2020 | 연락처 | 링크모음 | 검색 | 사이트맵 |