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DM74AS874NT 데이터시트 PDF




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부품번호 DM74AS874NT 기능
기능 Dual 4-Bit D-Type Edge-Triggered Flip-Flop
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DM74AS874NT 데이터시트, 핀배열, 회로
October 1986
Revised March 2000
DM74AS874
Dual 4-Bit D-Type Edge-Triggered Flip-Flop
General Description
These dual 4-bit inverting registers feature totem-pole 3-
STATE outputs designed specifically for driving highly-
capacitive or relatively low-impedance loads. The high-
impedance state and increased high-logic-level drive pro-
vide these registers with the capability of being connected
directly to and driving the bus lines in a bus-organized sys-
tem without need for interface or pull-up components. They
are particularly attractive for implementing buffer registers,
I/O ports, bidirectional bus drivers, and working registers.
The eight flip-flops of the DM74AS874 are edge-triggered
D-type flip-flops. On the positive transition of the clock, the
Q outputs will be set to the logic states that were set up at
the D inputs.
A buffered output control input can be used to place the
eight outputs in either a normal logic state (HIGH or LOW
logic levels) or a high-impedance state. In the high-imped-
ance state the outputs neither load nor drive the bus lines
significantly.
The output control does not affect the internal operation of
the flip-flops. That is, the old data can be retained or new
data can be entered even while the outputs are OFF.
The pinout is arranged to ease printed circuit board layout.
All data inputs are on one side of the package, while all
outputs are on the other side.
Features
s Switching specifications at 50 pF
s Switching specifications guaranteed over full tempera-
ture and VCC range
s Advanced oxide-isolated, ion-implanted Schottky TTL
process
s 3-STATE buffer-type outputs drive bus lines directly
s Space saving 300 mil wide package
s Bus structured pinout
Ordering Code:
Order Number Package Number
Package Description
DM74AS874WM
M24B
24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
DM74AS874NT
N24C
24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-100, 0.300 Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagram
© 2000 Fairchild Semiconductor Corporation DS006331
www.fairchildsemi.com




DM74AS874NT pdf, 반도체, 판매, 대치품
Switching Characteristics
over recommended operating free air temperature range
Symbol
Parameter
Conditions
fMAX
tPLH
tPHL
Maximum Clock Frequency
Propagation Delay Time
LOW-to-HIGH Level Output
Propagation Delay Time
HIGH-to-LOW Level Output
VCC = 4.5V to 5.5V
RL = 500
CL = 50 pF
tPZH Output Enable Time
to HIGH Level Output
tPZL Output Enable Time
to LOW Level Output
tPHZ Output Disable Time
from HIGH Level Output
tPLZ Output Disable Time
from LOW Level Output
tPHL Propagation Delay Time
HIGH-to-LOW Level Output
From
To
Clock
Clock
Any Q
Any Q
Output Control Any Q
Output Control Any Q
Output Control Any Q
Output Control Any Q
Clear
Any Q
Min
Max
Units
80 MHz
3 8.5 ns
4 10.5 ns
2 7 ns
3 10.5 ns
2 6 ns
2 7.5 ns
4 11.5 ns
www.fairchildsemi.com
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관련 데이터시트

부품번호상세설명 및 기능제조사
DM74AS874NT

Dual 4-Bit D-Type Edge-Triggered Flip-Flop

Fairchild Semiconductor
Fairchild Semiconductor

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