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부품번호 DM74LS139SJ 기능
기능 Decoder/Demultiplexer
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DM74LS139SJ 데이터시트, 핀배열, 회로
August 1986
Revised March 2000
DM74LS138 • DM74LS139
Decoder/Demultiplexer
General Description
These Schottky-clamped circuits are designed to be used
in high-performance memory-decoding or data-routing
applications, requiring very short propagation delay times.
In high-performance memory systems these decoders can
be used to minimize the effects of system decoding. When
used with high-speed memories, the delay times of these
decoders are usually less than the typical access time of
the memory. This means that the effective system delay
introduced by the decoder is negligible.
The DM74LS138 decodes one-of-eight lines, based upon
the conditions at the three binary select inputs and the
three enable inputs. Two active-low and one active-high
enable inputs reduce the need for external gates or invert-
ers when expanding. A 24-line decoder can be imple-
mented with no external inverters, and a 32-line decoder
requires only one inverter. An enable input can be used as
a data input for demultiplexing applications.
The DM74LS139 comprises two separate two-line-to-four-
line decoders in a single package. The active-low enable
input can be used as a data line in demultiplexing applica-
tions.
All of these decoders/demultiplexers feature fully buffered
inputs, presenting only one normalized load to its driving
circuit. All inputs are clamped with high-performance
Schottky diodes to suppress line-ringing and simplify sys-
tem design.
Features
s Designed specifically for high speed:
Memory decoders
Data transmission systems
s DM74LS138 3-to-8-line decoders incorporates 3 enable
inputs to simplify cascading and/or data reception
s DM74LS139 contains two fully independent 2-to-4-line
decoders/demultiplexers
s Schottky clamped for high performance
s Typical propagation delay (3 levels of logic)
DM74LS138 21 ns
DM74LS139 21 ns
s Typical power dissipation
DM74LS138 32 mW
DM74LS139 34 mW
Ordering Code:
Order Number Package Number
Package Description
DM74LS138M
M16A
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow
DM74LS138SJ
M16D
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
DM74LS138N
N16E
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
DM74LS139M
M16A
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow
DM74LS139SJ
M16D
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
DM74LS139N
N16E
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
© 2000 Fairchild Semiconductor Corporation DS006391
www.fairchildsemi.com




DM74LS139SJ pdf, 반도체, 판매, 대치품
DM74LS139 Recommended Operating Conditions
Symbol
VCC
VIH
VIL
IOH
IOL
TA
Parameter
Supply Voltage
HIGH Level Input Voltage
LOW Level Input Voltage
HIGH Level Output Current
LOW Level Output Current
Free Air Operating Temperature
Min
4.75
2
Nom
5
0
DM74LS139 Electrical Characteristics
over recommended operating free air temperature range (unless otherwise noted)
Symbol
Parameter
Conditions
Min
VI Input Clamp Voltage
VCC = Min, II = −18 mA
VOH HIGH Level
VCC = Min, IOH = Max,
Output Voltage
VIL = Max, VIH = Min
VOL LOW Level
VCC = Min, IOL = Max
Output Voltage
VIL = Max, VIH = Min
IOL = 4 mA, VCC = Min
II
Input Current @ Max Input Voltage
VCC = Max, VI = 7V
IIH HIGH Level Input Current
VCC = Max, VI = 2.7V
IIL LOW Level Input Current
VCC = Max, VI = 0.4V
IOS Short Circuit Output Current
VCC = Max (Note 7)
ICC Supply Current
VCC = Max (Note 8)
2.7
20
Note 6: All typicals are at VCC = 5V, TA = 25°C.
Note 7: Not more than one output should be shorted at a time, and the duration should not exceed one second.
Note 8: ICC is measured with all outputs enabled and OPEN.
Max
Units
5.25
V
V
0.8 V
0.4
mA
8 mA
70 °C
Typ
(Note 6)
3.4
Max
1.5
0.35
0.25
6.8
0.5
0.4
0.1
20
0.36
100
11
Units
V
V
V
mA
µA
mA
mA
mA
DM74LS139 Switching Characteristics
at VCC = 5V and TA = 25°C
From (Input)
Symbol
Parameter
To (Output)
tPLH Propagation Delay Time
LOW-to-HIGH Level Output
tPHL Propagation Delay Time
HIGH-to-LOW Level Output
tPLH Propagation Delay Time
LOW-to-HIGH Level Output
tPHL Propagation Delay Time
HIGH-to-LOW Level Output
Select to Output
Select to Output
Enable to Output
Enable to Output
RL = 2 k
CL = 15 pF
CL = 50 pF
Min Max Min Max
18 27
27 40
18 27
24 40
Units
ns
ns
ns
ns
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DM74LS139SJ 전자부품, 판매, 대치품
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Package Number N16E
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
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부품번호상세설명 및 기능제조사
DM74LS139SJ

Decoder/Demultiplexer

Fairchild Semiconductor
Fairchild Semiconductor

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