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DM74LS161AM 데이터시트 PDF




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부품번호 DM74LS161AM 기능
기능 Synchronous 4-Bit Binary Counters
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DM74LS161AM 데이터시트, 핀배열, 회로
August 1986
Revised April 2000
DM74LS161A • DM74LS163A
Synchronous 4-Bit Binary Counters
General Description
These synchronous, presettable counters feature an inter-
nal carry look-ahead for application in high-speed counting
designs. The DM74LS161A and DM74LS163A are 4-bit
binary counters. The carry output is decoded by means of
a NOR gate, thus preventing spikes during the normal
counting mode of operation. Synchronous operation is pro-
vided by having all flip-flops clocked simultaneously so that
the outputs change coincident with each other when so
instructed by the count-enable inputs and internal gating.
This mode of operation eliminates the output counting
spikes which are normally associated with asynchronous
(ripple clock) counters. A buffered clock input triggers the
four flip-flops on the rising (positive-going) edge of the
clock input waveform.
These counters are fully programmable; that is, the outputs
may be preset to either level. As presetting is synchronous,
setting up a low level at the load input disables the counter
and causes the outputs to agree with the setup data after
the next clock pulse, regardless of the levels of the enable
input. The clear function for the DM74LS161A is asynchro-
nous; and a low level at the clear input sets all four of the
flip-flop outputs LOW, regardless of the levels of clock,
load, or enable inputs. The clear function for the
DM74LS163A is synchronous; and a low level at the clear
inputs sets all four of the flip-flop outputs LOW after the
next clock pulse, regardless of the levels of the enable
inputs. This synchronous clear allows the count length to
be modified easily, as decoding the maximum count
desired can be accomplished with one external NAND
gate. The gate output is connected to the clear input to
synchronously clear the counter to all low outputs.
The carry look-ahead circuitry provides for cascading
counters for n-bit synchronous applications without addi-
tional gating. Instrumental in accomplishing this function
are two count-enable inputs and a ripple carry output.
Both count-enable inputs (P and T) must be HIGH to count,
and input T is fed forward to enable the ripple carry output.
The ripple carry output thus enabled will produce a high-
level output pulse with a duration approximately equal to
the high-level portion of the QA output. This high-level over-
flow ripple carry pulse can be used to enable successive
cascaded stages. HIGH-to-LOW level transitions at the
enable P or T inputs may occur, regardless of the logic
level of the clock.
These counters feature a fully independent clock circuit.
Changes made to control inputs (enable P or T or load) that
will modify the operating mode have no effect until clocking
occurs. The function of the counter (whether enabled, dis-
abled, loading, or counting) will be dictated solely by the
conditions meeting the stable set-up and hold times.
Features
s Synchronously programmable
s Internal look-ahead for fast counting
s Carry output for n-bit cascading
s Synchronous counting
s Load control line
s Diode-clamped inputs
s Typical propagation time, clock to Q output 14 ns
s Typical clock frequency 32 MHz
s Typical power dissipation 93 mW
Ordering Code:
Order Number Package Number
Package Description
DM74LS161AM
M16A
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow
DM74LS161AN
N16E
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
DM74LS163AM
M16A
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow
DM74LS163AN
N16E
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
© 2000 Fairchild Semiconductor Corporation DS006397
www.fairchildsemi.com




DM74LS161AM pdf, 반도체, 판매, 대치품
Timing Diagram
LS161A, LS163A Synchronous Binary Counters
Typical Clear, Preset, Count and Inhibit Sequences
Sequence:
(1) Clear outputs to zero
(2) Preset to binary twelve
(3) Count to thirteen, fourteen, fifteen, zero, one, and two
(4) Inhibit
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DM74LS161AM 전자부품, 판매, 대치품
DM74LS163A Recommended Operating Conditions
Symbol
VCC
VIH
VIL
IOH
IOL
fCLK
tW
Parameter
Supply Voltage
HIGH Level Input Voltage
LOW Level Input Voltage
HIGH Level Output Current
LOW Level Output Current
Clock Frequency (Note 8)
Clock Frequency (Note 9)
Pulse Width
Clock
(Note 8)
Clear
Min
4.75
2
0
0
20
20
Nom
5
6
9
Max
5.25
0.8
0.4
8
25
20
Pulse Width
(Note 9)
Clock
Clear
25
25
tSU Setup Time
(Note 8)
Data
Enable P
20 8
25 17
Setup Time
Load
Data
25 15
20
(Note 9)
Enable P
30
tH Hold Time
(Note 8)
Hold Time
Load
Data
Others
Data
30
0 3
0 3
5
(Note 9)
Others
tREL Clear Release Time (Note 8)
Clear Release Time (Note 9)
5
20
25
TA Free Air Operating Temperature
Note 8: CL = 15 pF, RL = 2 k, TA = 25°C and VCC = 5V.
Note 9: CL = 50 pF, RL = 2 k, TA = 25°C and VCC = 5V.
0
70
DM74LS163A Electrical Characteristics
over recommended operating free air temperature range (unless otherwise noted)
Symbol
Parameter
Conditions
VI Input Clamp Voltage
VOH HIGH Level
Output Voltage
VOL LOW Level
Output Voltage
II Input Current @ Max
Input Voltage
VCC = Min, II = −18 mA
VCC = Min, IOH = Max
VIL = Max, VIH = Min
VCC = Min, IOL = Max
VIL = Max, VIH = Min
IOL = 4 mA, VCC = Min
VCC = Max
VI = 7V
Enable T
Clock, Clear
Load
Min
2.7
Typ
(Note 10)
3.4
0.35
0.25
Max
1.5
0.5
0.4
0.2
0.2
0.2
IIH HIGH Level
Input Current
VCC = Max
VI = 2.7V
Others
Enable T
Load
Clock, Clear
0.1
40
40
40
Others
20
IIL LOW Level
Input Current
VCC = Max
VI = 0.4V
Enable T
Clock, Clear
Load
0.8
0.8
0.8
Others
0.4
IOS
Short Circuit Output Current
VCC = Max (Note 11)
20 100
ICCH
Supply Current with Outputs HIGH VCC = Max (Note 12)
18 31
ICCL Supply Current with Outputs LOW VCC = Max (Note 13)
18 32
Note 10: All typicals are at VCC = 5V, TA = 25°C.
Note 11: Not more than one output should be shorted at a time, and the duration should not exceed one second.
Note 12: ICCH is measured with the load HIGH, then again with the load LOW, with all other inputs HIGH and all outputs OPEN.
Note 13: ICCL is measured with the clock input HIGH, then again with the clock input LOW, with all other inputs LOW and all outputs OPEN.
Units
V
V
V
mA
mA
MHz
MHz
ns
ns
ns
ns
ns
ns
ns
ns
°C
Units
V
V
V
mA
µA
mA
mA
mA
mA
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