DataSheet.es    


PDF AX88140AQ Data sheet ( Hoja de datos )

Número de pieza AX88140AQ
Descripción Fast Ethernet MAC Controller
Fabricantes ETC　
Logotipo ETC Logotipo



Hay una vista previa y un enlace de descarga de AX88140AQ (archivo pdf) en la parte inferior de esta página.


Total 46 Páginas

No Preview Available ! AX88140AQ Hoja de datos, Descripción, Manual

ASIX
AX88140A
Fast Ethernet MAC Controller
ASIX AX88140A
100BASE-TX/FX PCI Bus
Fast Ethernet MAC Controller
Data Sheet(11/03/’97)
DOCUMENT NO. : AX140D2.DOC
This data sheets contain new products information. ASIX ELECTRONICS reserves the rights to modify the products
specification without notice. No liability is assumed as a result of the use of this product. No rights under any patent
accompany the sale of the product.
ASIX ELECTRONICS CORPORATION
2F, NO.13, Industry East Rd. II, Science-based Industrial Park, Hsin-Chu City, Taiwan, R.O.C.
TEL: 886-3-579-9500
FAX: 886-3-579-9558

1 page




AX88140AQ pdf
AX88140A
PRELIMINARY
TABLES
TAB - 1 PCI INTERFACE GROUP ................................................................................................................................... 13
TAB - 2 BOOT ROM , SERIAL ROM , GENERAL-PURPOSE SIGNALS GROUP................................................................. 14
TAB - 3 MII/SYM/SRL INTERFACE SIGNALS GROUP ................................................................................................... 15
TAB - 4 EXTENDED , NC, POWER PINS GROUP ............................................................................................................. 16
TAB - 5 CONFIGURATION SPACE MAPPING .................................................................................................................. 17
TAB - 6 CSID CONFIGURATION ID REGISTER DESCRIPTION ....................................................................................... 18
TAB - 7 CSCS COMMAND AND STATUS CONFIGURATION REGISTER........................................................................... 18
TAB - 8 CSRV CONFIGURATION REVISION REGISTER DESCRIPTION ........................................................................... 18
TAB - 9 CSLT CONFIGURATION ID REGISTER DESCRIPTION ...................................................................................... 18
TAB - 10 CBIO CONFIGURATION BASE I/O ADDRESS REGISTER DESCRIPTION .......................................................... 19
TAB - 11 CBMA CONFIGURATION BASE MEMORY ADDRESS REGISTER DESCRIPTION............................................... 19
TAB - 12 CBER EXPANSION ROM BASE ADDRESS REGISTER DESCRIPTION .............................................................. 19
TAB - 13 CSIT CONFIGURATION INTERRUPT REGISTER DESCRIPTION ........................................................................ 19
TAB - 14 COMMAND AND STATUS REGISTER MAPPING ............................................................................................... 20
TAB - 15 REG0 BUS MODE REGISTER DESCRIPTION................................................................................................... 21
TAB - 16 REG1 TRANSMIT POLL DEMAND REGISTER DESCRIPTION ........................................................................... 21
TAB - 17 REG2 RECEIVE POLL DEMAND REGISTER DESCRIPTION.............................................................................. 22
TAB - 18 REG3 RECEIVE LIST BASE ADDRESS REGISTER DESCRIPTION ..................................................................... 22
TAB - 19 REG4 TRANSMIT LIST BASE ADDRESS REGISTER DESCRIPTION .................................................................. 22
TAB - 20 REG5 STATUS REGISTER DESCRIPTION........................................................................................................ 24
TAB - 21 REG6 OPERATION MODE REGISTER DESCRIPTION....................................................................................... 25
TAB - 22 PORT AND DATA RATE SELECTION ............................................................................................................... 25
TAB - 23 REG7 INTERRUPT ENABLE REGISTER DESCRIPTION..................................................................................... 26
TAB - 24 REG8 MISSED FRAME AND OVERFLOW COUNTER DESCRIPTION ................................................................. 26
TAB - 25 REG9 SERIAL ROM, AND MII MANAGEMENT REGISTER DESCRIPTION ..................................................... 27
TAB - 26 REG11 GENERAL-PURPOSE TIMER REGISTER DESCRIPTION........................................................................ 28
TAB - 27 REG12 GENERAL-PURPOSE PORT REGISTER DESCRIPTION.......................................................................... 28
TAB - 28 REG13 FILTERING INDEX REGISTER DESCRIPTION ...................................................................................... 28
TAB - 29 REG14 FILTERING DATA REGISTER DESCRIPTION ....................................................................................... 28
TAB - 30 DESCRIPTION OF FILTERING BUFFER ............................................................................................................ 28
TAB - 31 LAYOUT OF FILTERING BUFFER .................................................................................................................... 29
TAB - 32 RECEIVE DESCRIPTOR 0 ................................................................................................................................ 32
TAB - 33 RECEIVE DESCRIPTOR 1 ................................................................................................................................ 32
TAB - 34 RECEIVE DESCRIPTOR 2 ................................................................................................................................ 32
TAB - 35 RECEIVE DESCRIPTOR 3 ................................................................................................................................ 32
TAB - 36 TRANSMIT DESCRIPTOR 0 ............................................................................................................................. 34
TAB - 37 TRANSMIT DESCRIPTOR 1 ............................................................................................................................. 34
TAB - 38 TRANSMIT DESCRIPTOR 2 ............................................................................................................................. 34
TAB - 39 TRANSMIT DESCRIPTOR 3 ............................................................................................................................. 34
5 ASIX ELECTRONICS CORPORATION

5 Page





AX88140AQ arduino
AX88140A
PRELIMINARY
2.0 Signal Description
2.1 Signal Descriptions for 160-pin and 144-pin
The following terms describe the AX88140A pin-out:
l Address phase
Address and appropriate bus commands are driven during this cycle.
l Data phase
Data and the appropriate byte enable codes are driven during this cycle.
l#
All pin names with the # suffix are asserted low.
The following abbreviations are used in Tab - 1 PCI interface group Tab - 2 Boot ROM , Serial ROM , General-
purpose signals group ,Tab - 3 MII/SYM/SRL interface signals group ,Tab - 4 Extended , NC, Power pins group..
I Input
O Output
I/O Input /Output
O/D Open Drain
11 ASIX ELECTRONICS CORPORATION

11 Page







PáginasTotal 46 Páginas
PDF Descargar[ Datasheet AX88140AQ.PDF ]




Hoja de datos destacado

Número de piezaDescripciónFabricantes
AX88140AFast Ethernet MAC ControllerETC
ETC
AX88140APFast Ethernet MAC ControllerETC
ETC
AX88140AQFast Ethernet MAC ControllerETC
ETC

Número de piezaDescripciónFabricantes
SLA6805M

High Voltage 3 phase Motor Driver IC.

 Sanken
Sanken
SDC1742

12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters.

 Analog Devices
Analog Devices


DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares,
permitiéndote verlos en linea o descargarlos en PDF.


DataSheet.es    |   2020   |  Privacy Policy  |  Contacto  |  Buscar