|
|
|
부품번호 | AZ100LVEL16VRLR1 기능 |
|
|
기능 | ECL/PECL Oscillator Gain Stage & Buffer with Selectable Enable | ||
제조업체 | ETC | ||
로고 | |||
ARIZONA MICROTEK, INC.
AZ100LVEL16VR
ECL/PECL Oscillator Gain Stage & Buffer with Selectable Enable
FEATURES
• High Bandwidth for ≥1GHz
• Similar Operation as AZ100EL16VO
• Operating Range of 3.0V to 5.5V
• Minimizes External Components
• Selectable Enable Polarity and Threshold
(CMOS/TTL or PECL)
• Available in a 3x3mm MLP Package
DESCRIPTION
PACKAGE AVAILABILITY
PACKAGE
MLP 16
MLP 16 T&R
MLP 16 T&R
DIE
PART NO.
AZ100LVEL16VRL
AZ100LVEL16VRLR1
AZ100LVEL16VRLR2
AZ100LVEL16VRX
MARKING
AZM16R
AZM16R
AZM16R
N/A
The AZ100LVEL16VR is a specialized oscillator gain stage with high gain output buffer including an enable.
The QHG/Q¯ HG outputs have a voltage gain several times greater than the Q/Q¯ outputs.
The AZ100LVEL16VR provides a selectable enable that allows continuous oscillator operation. See truth table
below for enable function. If Enable pull-up is desired in the CMOS mode, an external ≤20kΩ resistor connecting
EN to VCC will override the on-chip pull-down resistor. The AZ100LVEL16VR also provides a VBB and 470Ω
internal bias resistors from D to VBB and D¯ to VBB. The VBB pin can support 1.5mA sink/source current. Bypassing
VBB to ground with a 0.01 µF capacitor is recommended.
Outputs Q/Q¯ each have a selectable on-chip pull-down current source. See truth table below for current source
functions. External resistors may also be used to increase pull-down current to a maximum total of 25mA.
Outputs QHG/Q¯ HG each have an optional on-chip pull-down current source of 10mA. When pad/pin VEEP is left
open (NC), the output current sources are disabled and the QHG /Q¯ HG operate as standard PECL/ECL. When VEEP is
connected to VEE , the current sources are activated. The QHG /Q¯ HG pull-down current can be decreased, by using a
resistor to connect from VEEP to VEE.
NOTE: Specifications in the ECL/PECL tables are valid when thermal equilibrium is established.
1630 S. STAPLEY DR., SUITE 125 • MESA, ARIZONA 85204 • USA • (480) 962-5881 • FAX (480) 890-2541
www.azmicrotek.com
AZ100LVEL16VR
D
{EN
EN-SEL OPEN
EN-SEL SHORTED TO VEE
Q
QHG
TIMING DIAGRAM
(PECL)
(CMOS)
Q Q NC VCC
16 15 14 13
NC 1
12 CS-SEL
D2
D3
16MLP
11 QHG
10 QHG
VBB 4
9 EN-SEL
5 678
EN NC VEE VEEP
TOP VIEW
LV16VR
DA
Q
M
Q VCC
LK
D
VBB
J
B DIE: 950u X 950u
BOND PAD: 85u X 85u I
C THICKNESS: 14mils H
EN D
EF
G
CS-SEL
QHG
QHG
EN-SEL
VEE VEEP
July 2002 * REV - 1
www.azmicrotek.com
4
4페이지 | |||
구 성 | 총 6 페이지수 | ||
다운로드 | [ AZ100LVEL16VRLR1.PDF 데이터시트 ] |
당사 플랫폼은 키워드, 제품 이름 또는 부품 번호를 사용하여 검색할 수 있는 |
구매 문의 | 일반 IC 문의 : 샘플 및 소량 구매 ----------------------------------------------------------------------- IGBT, TR 모듈, SCR 및 다이오드 모듈을 포함한 광범위한 전력 반도체를 판매합니다. 전력 반도체 전문업체 상호 : 아이지 인터내셔날 사이트 방문 : [ 홈페이지 ] [ 블로그 1 ] [ 블로그 2 ] |
부품번호 | 상세설명 및 기능 | 제조사 |
AZ100LVEL16VRLR1 | ECL/PECL Oscillator Gain Stage & Buffer with Selectable Enable | ETC |
AZ100LVEL16VRLR2 | ECL/PECL Oscillator Gain Stage & Buffer with Selectable Enable | ETC |
DataSheet.kr | 2020 | 연락처 | 링크모음 | 검색 | 사이트맵 |