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기능 CMOS High Performance Programmable DMA Controller
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5962-9054301MQA 데이터시트, 핀배열, 회로
SEMICONDUCTOR
82C37A
March 1997
CMOS High Performance
Programmable DMA Controller
Features
Description
• Compatible with the NMOS 8237A
• Four Independent Maskable Channels with Autoinitial-
ization Capability
• Cascadable to any Number of Channels
• High Speed Data Transfers:
- Up to 4MBytes/sec with 8MHz Clock
- Up to 6.25MBytes/sec with 12.5MHz Clock
• Memory-to-Memory Transfers
• Static CMOS Design Permits Low Power Operation
- ICCSB = 10µA Maximum
- ICCOP = 2mA/MHz Maximum
• Fully TTL/CMOS Compatible
• Internal Registers may be Read from Software
The 82C37A is an enhanced version of the industry standard
8237A Direct Memory Access (DMA) controller, fabricated
using Harris’ advanced 2 micron CMOS process. Pin
compatible with NMOS designs, the 82C37A offers
increased functionality, improved performance, and
dramatically reduced power consumption. The fully static
design permits gated clock operation for even further
reduction of power.
The 82C37A controller can improve system performance by
allowing external devices to transfer data directly to or from
system memory. Memory-to-memory transfer capability is
also provided, along with a memory block initialization fea-
ture. DMA requests may be generated by either hardware or
software, and each channel is independently programmable
with a variety of features for flexible operation.
The 82C37A is designed to be used with an external
address latch, such as the 82C82, to demultiplex the most
significant 8-bits of address. The 82C37A can be used with
industry standard microprocessors such as 80C286, 80286,
80C86, 80C88, 8086, 8088, 8085, Z80, NSC800, 80186 and
others. Multimode programmability allows the user to select
from three basic types of DMA services, and reconfiguration
under program control is possible even with the clock to the
controller stopped. Each channel has a full 64K address and
word count range, and may be programmed to autoinitialize
these registers following DMA termination (end of process).
Ordering Information
5MHz
CP82C37A-5
IP82C37A-5
CS82C37A-5
IS82C37A-5
CD82C37A-5
ID82C37A-5
MD82C37A-5/B
5962-9054301MQA
MR82C37A-5/B
5962-9054301MXA
PART NUMBER
8MHz
CP82C37A
IP82C37A
CS82C37A
IS82C37A
CD82C37A
ID82C37A
MD82C37A/B
5962-9054302MQA
MR82C37A/B
5962-9054302MXA
12.5MHz
CP82C37A-12
IP82C37A-12
CS82C37A-12
IS82C37A-12
CD82C37A-12
ID82C37A-12
MD82C37A-12/B
5962-9054303MQA
MR82C37A-12/B
5962-9054303MXA
PACKAGE
40 Ld PDIP
44 Ld PLCC
40 Ld CERDIP
SMD#
44 Pad CLCC
SMD#
TEMPERATURE
RANGE
0oC to +70oC
-40oC to +85oC
0oC to +70oC
-40oC to +85oC
0oC to +70oC
-40oC to +85oC
-55oC to +125oC
-55oC to +125oC
PKG. NO.
E40.6
E40.6
N44.65
N44.65
F40.6
F40.6
F40.6
F40.6
J44.A
J44.A
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright © Harris Corporation 1997
4-192
File Number 2967.1




5962-9054301MQA pdf, 반도체, 판매, 대치품
82C37A
Pin Description (Continued)
PIN
SYMBOL NUMBER TYPE
DESCRIPTION
EOP
36 I/O END OF PROCESS: End of Process (EOP) is an active low bidirectional signal. Information
concerning the completion of DMA services is available at the bidirectional EOP pin.
The 82C37A allows an external signal to terminate an active DMA service by pulling the EOP pin
low. A pulse is generated by the 82C37A when terminal count (TC) for any channel is reached,
except for channel 0 in memory-to-memory mode. During memory-to-memory transfers, EOP will
be output when the TC for channel 1 occurs.
The EOP pin is driven by an open drain transistor on-chip, and requires an external pull-up resistor
to VCC.
When an EOP pulse occurs, whether internally or externally generated, the 82C37A will terminate
the service, and if autoinitialize is enabled, the base registers will be written to the current registers
of that channel. The mask bit and TC bit in the status word will be set for the currently active channel
by EOP unless the channel is programmed for autoinitialize. In that case, the mask bit remains clear.
A0-A3
32-35
I/O ADDRESS: The four least significant address lines are bidirectional three-state signals. In the Idle
cycle, they are inputs and are used by the 82C37A to address the control register to be loaded or
read. In the Active cycle, they are outputs and provide the lower 4-bits of the output address.
A4-A7
37-40
O ADDRESS: The four most significant address lines are three-state outputs and provide 4-bits of
address. These lines are enabled only during the DMA service.
HRQ 10 O HOLD REQUEST: The Hold Request (HRQ) output is used to request control of the system bus.
When a DREQ occurs and the corresponding mask bit is clear, or a software DMA request is made,
the 82C37A issues HRQ. The HLDA signal then informs the controller when access to the system
busses is permitted. For stand-alone operation where the 82C37A always controls the busses, HRQ
may be tied to HLDA. This will result in one S0 state before the transfer.
DACK0-
DACK3
14, 15
24, 25
O DMA ACKNOWLEDGE: DMA acknowledge is used to notify the individual peripherals when one
has been granted a DMA cycle. The sense of these lines is programmable. RESET initializes them
to active low.
AEN 9 O ADDRESS ENABLE: Address Enable enables the 8-bit latch containing the upper 8 address bits
onto the system address bus. AEN can also be used to disable other system bus drivers during DMA
transfers. AEN is active high.
ADSTB
8
O ADDRESS STROBE: This is an active high signal used to control latching of the upper address
byte. It will drive directly the strobe input of external transparent octal latches, such as the 82C82.
During block operations, ADSTB will only be issued when the upper address byte must be updated,
thus speeding operation through elimination of S1 states. ADSTB timing is referenced to the falling
edge of the 82C37A clock.
MEMR
3
O MEMORY READ: The Memory Read signal is an active low three-state output used to access data
from the selected memory location during a DMA Read or a memory-to-memory transfer.
MEMW
4
O MEMORY WRITE: The Memory Write signal is an active low three-state output used to write data
to the selected memory location during a DMA Write or a memory-to-memory transfer.
NC 5
NO CONNECT: Pin 5 is open and should not be tested for continuity.
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5962-9054301MQA 전자부품, 판매, 대치품
82C37A
the initial 82C37A.This allows the DMA requests of the
additional device to propagate through the priority network
circuitry of the preceding device. The priority chain is
preserved and the new device must wait for its turn to
acknowledge requests. Since the cascade channel of the
initial 82C37A is used only for prioritizing the additional
device, it does not output an address or control signals of its
own. These could conflict with the outputs of the active chan-
nel in the added device. The initial 82C37A will respond to
DREQ and generate DACK but all other outputs except HRQ
will be disabled. An external EOP will be ignored by the initial
device, but will have the usual effect on the added device.
Figure 3 shows two additional devices cascaded with an
initial device using two of the initial device’s channels. This
forms a two-level DMA system. More 82C37As could be
added at the second level by using the remaining channels
of the first level. Additional devices can also be added by
cascading into the channels of the second level devices,
forming a third level.
Autoinitialize - By setting bit 4 in the Mode register, a
channel may be set up as an Autoinitialize channel. During
Autoinitialization, the original values of the Current Address
and Current Word Count registers are automatically restored
from the Base Address and Base Word Count registers of
the channel following EOP. The base registers are loaded
simultaneously with the current registers by the micropro-
cessor and remain unchanged throughout the DMA service.
The mask bit is not set when the channel is in Autoinitialize
mode. Following Autoinitialization, the channel is ready to
perform another DMA service, without CPU intervention, as
soon as a valid DREQ is detected, or software request
made.
Memory-to-Memory - To perform block moves of data from
one memory address space to another with minimum of
program effort and time, the 82C37A includes a memory-to-
memory transfer feature. Setting bit 0 in the Command
register selects channels 0 and 1 to operate as memory-to-
memory transfer channels.
80C86/88
MICRO-
PROCESSOR
1ST LEVEL
HRQ DREQ
HLDA DACK
82C37A
DREQ
DACK
INITIAL DEVICE
2ND LEVEL
82C37A
HRQ
HLDA
HRQ
HLDA
82C37A
The transfer is initiated by setting the software or hardware
DREQ for channel 0. The 82C37A requests a DMA service
in the normal manner. After HLDA is true, the device, using
four-state transfers in Block Transfer mode, reads data from
the memory. The channel 0 Current Address register is the
source for the address used and is decremented or
incremented in the normal manner. The data byte read from
the memory is stored in the 82C37A internal Temporary reg-
ister. Another four-state transfer moves the data to memory
using the address in channel one’s Current Address register
and incrementing or decrementing it in the normal manner.
The channel 1 Current Word Count is decremented.
ADDITIONAL
DEVICES
FIGURE 3. CASCADED 82C37As
When programming cascaded controllers, start with the first
level device (closest to the microprocessor). After RESET,
the DACK outputs are programmed to be active low and are
held in the high state. If they are used to drive HLDA directly,
the second level device(s) cannot be programmed until
DACK polarity is selected as active high on the initial device.
Also, the initial device’s mask bits function normally on
cascaded channels, so they may be used to inhibit second-
level services.
Transfer Types
Each of the three active transfer modes can perform three dif-
ferent types of transfers. These are Read, Write and Verify.
Write transfers move data from an I/O device to the memory
by activating MEMW and IOR. Read transfers move data from
memory to an I/O device by activating MEMR and IOW.
Verify transfers are pseudo-transfers. The 82C37A operates
as in Read or Write transfers generating addresses and
responding to EOP, etc., however the memory and I/O
control lines all remain inactive. Verify mode is not permitted
for memory-to-memory operation. READY is ignored during
Verify transfers.
When the word count of channel 1 decrements to FFFFH, a
TC is generated causing an EOP output, terminating the
service, and setting the channel 1 TC bit in the Status
register. The channel 1 mask bit will also be set, unless the
channel 1 mode register is programmed for autoinitialization.
Channel 0 word count decrementing to FFFFH will not set
the channel 0 TC bit in the status register nor generate an
EOP, nor set the channel 0 mask bit in this mode. It will
cause an autoinitialization of channel 0, if that option has
been selected.
If full Autoinitialization for a memory-to-memory operation is
desired, the channel 0 and channel 1 word counts must be
set to equal values before the transfer begins. Otherwise, if
channel 0 underflows before channel 1, it will autoinitialize
and set the data source address back to the beginning of the
block. If the channel 1 word count underflows before channel
0, the memory-to-memory DMA service will terminate, and
channel 1 will autoinitialize but channel 0 will not.
In memory-to-memory mode, Channel 0 may be
programmed to retain the same address for all transfers.
This allows a single byte to be written to a block of memory.
This channel 0 address hold feature is selected by setting bit
1 in the Command register.
The 82C37A will respond to external EOP signals during
memory-to-memory transfers, but will only relinquish the
system busses after the transfer is complete (i.e. after an
4-198

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