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PDF 5962R9581801QJC Data sheet ( Hoja de datos )

Número de pieza 5962R9581801QJC
Descripción Radiation Hardened 8-Bit Input/Output Port
Fabricantes Intersil Corporation 
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HS-82C12RH
March 1996
Radiation Hardened
8-Bit Input/Output Port
Features
• Devices QML Qualified in Accordance with
MIL-PRF-38535
• Detailed Electrical and Screening Requirements are
Contained in SMD# 5962-95818 and Intersil’ QM Plan
- Radiation Hardened CMOS Process
- Total Dose 1 x 105 RAD (Si)
- Transient Upset > 1 x 108 RAD (Si)/s
- Latch-Up Immune EPI-CMOS > 1 x 1012 RAD (Si)/s
• Low Power Dissipation
• High Noise Immunity
• Single Power Supply +5V
• Low Input Load Current
• 8-Bit Data Register and Buffer
• Asynchronous Register Clear
• Service Request Flip-Flop for Interrupt Generation
• Three-State Outputs
• Bus-Compatible with HS-80C85RH CPU
• Electrically Equivalent to Sandia SA3026
• Military Temperature Range -55oC to +125oC
Functional Diagram
DS1
DS2
STB
CLR
MD
CONTROL
AND
DEVICE
SELECT
LOGIC
2
3
SERVICE
REQUEST
F.F.
DI0-7
DATA
LATCH
AND
BUFFER
(8)
DO0-7
Pin Description
PIN
DI0-DI7
DO0-DO7
DS1, DS2
DESCRIPTION
Data In
Data Out
Device Select
INT
Description
MD Mode
The Intersil HS-82C12RH is a radiation hardened 8-bit input/
output port designed for use with the HS-80C85RH radiation
hardened microprocessor. It is manufactured using a self-
aligned, junction-isolated EPI-CMOS process and features
three-state output buffers and device selection and control
logic. A service request flip-flop is included for the
generation and control of interrupts to the microprocessor.
The device can be used in implement many of the peripheral
and input/output functions of a microcomputer system. The
HS-82C12RH is pinout- and function- compatible with
industry-standard 8212 devices.
STB
INT
CLR
Strobe
Interrupt
Clear
Ordering Information
PART NUMBER
5962R9581801QJC
5962R9581801QXC
5962R9581801VJC
5962R9581801VXC
HS1-82C12RH/Sample
HS9-82C12RH/Sample
TEMPERATURE RANGE
-55oC to +125oC
-55oC to +125oC
-55oC to +125oC
-55oC to +125oC
+25oC
+25oC
SCREENING LEVEL
MIL-PRF-38535 Level Q
MIL-PRF-38535 Level Q
MIL-PRF-38535 Level V
MIL-PRF-38535 Level V
Sample
Sample
PACKAGE
24 Lead SBDIP
24 Lead Ceramic Flatpack
24 Lead SBDIP
24 Lead Ceramic Flatpack
24 Lead SBDIP
24 Lead Ceramic Flatpack
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999
1
Spec Number 518063
File Number 3041.2

1 page




5962R9581801QJC pdf
Timing Waveforms
(DS, DS2)
OUTPUT
HS-82C12RH
tE
tD
FIGURE 1. READ TIMING
0.5VDD
VOH
VOL
0.5VDD
DATA
MD OR (DS, DS2)
OUTPUT
tPW
tWE
tH
FIGURE 2. WRITE TIMING
DATA
STB OR (DS, DS2)
OUTPUT
tSET
tPD
tH
FIGURE 3. DATA SETUP, HOLD, PROPAGATION DELAY TIMING
STB
(DS, DS2)
INT
CLR
DO
tPW
tR
FIGURE 4. INTERRUPT TIMING
tPW
tC
FIGURE 5. CLEAR TIMING
5
tPW
tS
Spec Number 518063

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