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5962R9676601QYC 데이터시트 PDF




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부품번호 5962R9676601QYC 기능
기능 Radiation Hardened 256 x 8 CMOS RAM
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5962R9676601QYC 데이터시트, 핀배열, 회로
March 1996
HS-81C55RH,
HS-81C56RH
Radiation Hardened
256 x 8 CMOS RAM
Features
• Devices QML Qualified in Accordance with
MIL-PRF-38535
• Detailed Electrical and Screening Requirements are
Contained in SMD# 5962-95818 and Intersil’ QM Plan
• Radiation Hardened EPI-CMOS
- Parametrics Guaranteed 1 x 105 RAD(Si)
- Transient Upset > 1 x 108 RAD(Si)/s
- Latch-Up Free > 1 x 1012 RAD(Si)/s
• Electrically Equivalent to Sandia SA 3001
• Pin Compatible with Intel 8155/56
• Bus Compatible with HS-80C85RH
• Single 5V Power Supply
• Low Standby Current 200µA Max
• Low Operating Current 2mA/MHz
• Completely Static Design
• Internal Address Latches
• Two Programmable 8-Bit I/O Ports
• One Programmable 6-Bit I/O Port
• Programmable 14-Bit Binary Counter/Timer
• Multiplexed Address and Data Bus
• Self Aligned Junction Isolated (SAJI) Process
• Military Temperature Range -55oC to +125oC
Description
The HS-81C55/56RH are radiation hardened RAM and I/O
chips fabricated using the Intersil radiation hardened Self-
Aligned Junction Isolated (SAJI) silicon gate technology.
Latch-up free operation is achieved by the use of epitaxial
starting material to eliminate the parasitic SCR effect seen in
conventional bulk CMOS devices.
The HS-81C55/56RH is intended for use with the
HS-80C85RH radiation hardened microprocessor system. The
RAM portion is designed as 2048 static cells organized as 256
x 8. A maximum post irradiation access time of 500ns allows
the HS-81C55/56RH to be used with the HS-80C85RH CPU
without any wait states. The HS-81C55RH requires an active
low chip enable while the HS-81C56RH requires an active high
chip enable. These chips are designed for operation utilizing a
single 5V power supply.
Functional Diagram
IO/M
AD0 - AD7
CE OR CE
ALE
RD
WR
RESET
TIMER CLK
TIMER OUT
256 x 8
STATIC
RAM
PORT A
A 8 PA0 - PA7
PORT B
B 8 PB0 - PB7
TIMER
PORT C
C 8 PC0 - PC5
VDD (10V)
GND
81C55RH = CE
81C56RH = CE
Ordering Information
PART NUMBER
5962R9XXXX01QRC
5962R9XXXX01VRC
5962R9XXXX01QXC
5962R9XXXX01VXC
5962R9XXXX02QRC
5962R9XXXX02VRC
5962R9XXXX02QXC
5962R9XXXX02VXC
HS1-81C55RH/Sample
HS9-81C55RH/Sample
HS1-81C56RH/Sample
HS9-81C56RH/Sample
TEMPERATURE RANGE
-55oC to +125oC
-55oC to +125oC
-55oC to +125oC
-55oC to +125oC
-55oC to +125oC
-55oC to +125oC
-55oC to +125oC
-55oC to +125oC
+25oC
+25oC
+25oC
+25oC
SCREENING LEVEL
MIL-PRF-38535 Level Q
MIL-PRF-38535 Level V
MIL-PRF-38535 Level Q
MIL-PRF-38535 Level V
MIL-PRF-38535 Level Q
MIL-PRF-38535 Level V
MIL-PRF-38535 Level Q
MIL-PRF-38535 Level V
Sample
Sample
Sample
Sample
PACKAGE
40 Lead SBDIP
40 Lead SBDIP
42 Lead Ceramic Flatpack
42 Lead Ceramic Flatpack
40 Lead SBDIP
40 Lead SBDIP
42 Lead Ceramic Flatpack
42 Lead Ceramic Flatpack
40 Lead SBDIP
42 Lead Ceramic Flatpack
40 Lead SBDIP
42 Lead Ceramic Flatpack
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999
1
Spec Number 518056
File Number 3039.1




5962R9676601QYC pdf, 반도체, 판매, 대치품
Specifications HS-81C55RH, HS-81C56RH
Absolute Maximum Ratings
Reliability Information
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +7.0V
Input, Output or I/O Voltage . . . . . . . . . . . . GND-0.3V to VDD+0.3V
Storage Temperature Range . . . . . . . . . . . . . . . . . -65oC to +150oC
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175oC
Lead Temperature (Soldering 10s) . . . . . . . . . . . . . . . . . . . . +300oC
Typical Derating Factor . . . . . . . . . . . . 2mA/MHz Increase in IDDOP
ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1
Thermal Resistance
θJA
SBDIP Package . . . . . . . . . . . . . . . . . . . . 40.0oC/W
Ceramic Flatpack Package . . . . . . . . . . . 45.0oC/W
Maximum Package Power Dissipation at +125oC
θJC
5.0oC/W
5.0oC/W
SBDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.25W
Ceramic Flatpack Package . . . . . . . . . . . . . . . . . . . . . . . . . 1.11W
If device power exceeds package dissipation capability, provide heat
sinking or derate linearly at the following rate:
SBDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25.0mW/oC
Ceramic Flatpack Package . . . . . . . . . . . . . . . . . . . . . 22.2mW/oC
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
Operating Conditions
Operating Voltage Range . . . . . . . . . . . . . . . . . . . +4.75V to +5.25V
Operating Temperature Range . . . . . . . . . . . . . . . . -55oC to +125oC
Input Low Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0V to +0.8V
Input High Voltage . . . . . . . . . . . . . . . . . . . . . . . . VDD -0.5V to VDD
TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS
PARAMETERS
High Input Leakage
Current
Low Input Leakage
Current
Low Output Voltage
High Output Voltage
Static Current
Dynamic Current
Functional Tests
SYMBOL
CONDITIONS
IIH VDD = 5.25V, VIN = 0V,
Pin under test = VDD
IIL VDD = 5.25V, VIN = 5.25V,
Pin under test = 0V
VOL VDD = 5.25V, IOL = 2mA
VOH VDD = 4.75V, IOH = 2mA
IDDSB VDD = 5.25V
IDDOP VDD = 5.25V, f = 1MHz
FT VDD = 4.75V and 5.25V,
VIH = VDD-0.5V, VIL = 0.8V
GROUP A
SUBGROUPS
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
7, 8A, 8B
TEMPERATURE
-55oC, +25oC,
+125oC
-55oC, +25oC,
+125oC
-55oC, +25oC,
+125oC
-55oC, +25oC,
+125oC
-55oC, +25oC,
+125oC
-55oC, +25oC,
+125oC
-55oC, +25oC,
+125oC
LIMITS
MIN MAX
-1
-1 -
- 0.5
4.25 -
- 200
-2
--
UNITS
µA
µA
V
V
µA
mA
-
NOTE: All devices are guaranteed at worst case limits and over radiation. Dynamic current is proportional to operating frequency (2mA/MHz).
TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS
PARAMETERS
Address Latch Setup Time
Address Hold Time After Latch
Latch to READ/WRITE Control
Valid Data Out From Read Control
Address Stable to Data Out Valid
Latch Enable Width
READ/WRITE Control to Latch
Enable
READ/WRITE Control Width
Data In to WRITE Setup Time
Data In Hold Time After WRITE
SYMBOL CONDITIONS
TAL Notes 1, 4
TLA Notes 1, 4
TLC Notes 1, 4
TRD Notes 1, 4
TAD Notes 1, 4
TLL Notes 1, 4
TCL Notes 1, 4,7
GROUP A
SUBGROUPS TEMPERATURE
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
-55oC TA +125oC
-55oC TA +125oC
-55oC TA +125oC
-55oC TA +125oC
-55oC TA +125oC
-55oC TA +125oC
-55oC TA +125oC
LIMITS
MIN MAX
60 -
60 -
200 -
- 250
- 500
200 -
20 -
UNITS
ns
ns
ns
ns
ns
ns
ns
TCC
TDW
TWD
Notes 1, 4
Notes 1, 4
Notes 1, 4
9, 10, 11
9, 10, 11
9, 10, 11
-55oC TA +125oC
-55oC TA +125oC
-55oC TA +125oC
250
200
25
-
-
-
ns
ns
ns
Spec Number 518056
4

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5962R9676601QYC 전자부품, 판매, 대치품
Waveforms (Continued)
HS-81C55RH, HS-81C56RH
STROBED INPUT
BF
STROBED
INTR
RD
INPUT DATA
FROM PORT
tSBF
tSS
tSI
tPSS
tPHS
tRBE
tRDI
STROBED OUTPUT
BF
STROBE
INTR
WR
OUTPUT DATA
TO PORT
tWBF
tWI
tWP
tSBE
tSI
Spec Number 518056
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부품번호상세설명 및 기능제조사
5962R9676601QYC

Radiation Hardened 256 x 8 CMOS RAM

Intersil Corporation
Intersil Corporation

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