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PDF 42S16800A Data sheet ( Hoja de datos )

Número de pieza 42S16800A
Descripción 16Meg x 8/ 8Meg x16 & 4Meg x 32 128-MBIT SYNCHRONOUS DRAM
Fabricantes Integrated Silicon Solution Inc 
Logotipo Integrated Silicon Solution  Inc Logotipo



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No Preview Available ! 42S16800A Hoja de datos, Descripción, Manual

IS42S81600A,
IS42S16800A,
IS42S32400A,
16Meg x 8, 8Meg x16 & 4Meg x 32
128-MBIT SYNCHRONOUS DRAM
ISSI®
PRELIMINARY INFORMATION
JANUARY 2005
FEATURES
• Clock frequency: 166,143,100 MHz
• Fully synchronous; all signals referenced to a
positive clock edge
• Internal bank for hiding row access/precharge
• Power supply
IS42S81600A
VDD VDDQ
3.3V 3.3V
IS42S16800A
3.3V 3.3V
IS42S32400A
3.3V 3.3V
• LVTTL interface
• Programmable burst length
– (1, 2, 4, 8, full page)
• Programmable burst sequence:
Sequential/Interleave
• Auto Refresh (CBR)
• Self Refresh with programmable refresh periods
• 4096 refresh cycles every 64 ms
• Random column address every clock cycle
• Programmable CAS latency (2, 3 clocks)
• Burst read/write and burst read/single write
operations capability
• Burst termination by burst stop and precharge
command
• Industrial Temperature Availability
• Lead-free Availability
OVERVIEW
ISSI's 128Mb Synchronous DRAM achieves high-speed
data transfer using pipeline architecture. All inputs and
outputs signals refer to the rising edge of the clock
input.The 128Mb SDRAM is organized as follows.
IS42S81600A
4M x8x4 Banks
54-pin TSOPII
IS42S16800A
2M x16x4 Banks
54-pin TSOPII
IS42S32400A
1M x32x4 Banks
86-pin TSOPII
KEY TIMING PARAMETERS
Parameter
Clk Cycle Time
CAS Latency = 3
CAS Latency = 2
Clk Frequency
CAS Latency = 3
CAS Latency = 2
Access Time from Clock
CAS Latency = 3
CAS Latency = 2
-6 -7 -10 Unit
6 7 10 ns
- 10 10 ns
166 143 100 Mhz
- 100 100 Mhz
5.4 5.4 7 ns
- 6 9 ns
Copyright © 2005 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any
time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are
advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
PRELIMINARYINFORMATION,Rev. 00C
01/20/05
1

1 page




42S16800A pdf
IS42S81600A, IS42S16800A, IS42S32400A
ISSI ®
PIN CONFIGURATIONS
86 pin TSOP - Type II for x32
VDD
I/O0
VDDQ
I/O1
I/O2
VSSQ
I/O3
I/O4
VDDQ
I/O5
I/O6
VSSQ
I/O7
NC
VDD
DQM0
WE
CAS
RAS
CS
A11
BA0
BA1
A10
A0
A1
A2
DQM2
VDD
NC
I/O16
VSSQ
I/O17
I/O18
VDDQ
I/O19
I/O20
VSSQ
I/O21
I/O22
VDDQ
I/O23
VDD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
86 VSS
85 I/O15
84 VSSQ
83 I/O14
82 I/O13
81 VDDQ
80 I/O12
79 I/O11
78 VSSQ
77 I/O10
76 I/O9
75 VDDQ
74 I/O8
73 NC
72 VSS
71 DQM1
70 NC
69 NC
68 CLK
67 CKE
66 A9
65 A8
64 A7
63 A6
62 A5
61 A4
60 A3
59 DQM3
58 VSS
57 NC
56 I/O31
55 VDDQ
54 I/O30
53 I/O29
52 VSSQ
51 I/O28
50 I/O27
49 VDDQ
48 I/O26
47 I/O25
46 VSSQ
45 I/O24
44 VSS
PIN DESCRIPTIONS
A0-A11
A0-A7
BA0, BA1
I/O0 to I/O31
CLK
CKE
CS
RAS
CAS
Row Address Input
Column Address Input
Bank Select Address
Data I/O
System Clock Input
Clock Enable
Chip Select
Row Address Strobe Command
Column Address Strobe Command
WE
DQM0-DQM3
VDD
Vss
VDDQ
VssQ
NC
Write Enable
x32 Input/Output Mask
Power
Ground
Power Supply for I/O Pin
Ground for I/O Pin
No Connection
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
PRELIMINARYINFORMATION Rev. 00C
01/20/05
5

5 Page





42S16800A arduino
IS42S81600A, IS42S16800A, IS42S32400A
ISSI ®
FUNCTIONAL TRUTH TABLE Continued:
Read with auto
Precharging
Precharge
Precharging
Write with Auto
Precharge
Precharging
Row Activating
CS RAS CAS WE
H× ×
×
LH H H
LH H L
LH L H
LH L L
LL
HH
LL
HL
LL L H
LL L L
××
LH H H
LH H L
LH L H
LH L L
LL
HH
LL
HL
LL L H
LL L L
H× × ×
LH H H
LH H L
LH L H
LH L L
LL
HH
LL
HL
LL L H
LL L L
H× ×
×
LH H H
LH H L
LH L H
LH L L
LL
HH
LL
HL
LL L H
LL L L
Address
×
x
×
BA, CA, A10
BA, CA, A10
BA, RA
BA, A10
×
OC, BA
×
×
×
BA, CA, A10
BA, CA, A10
BA, RA
BA, A10
×
OC, BA
×
×
×
BA, CA, A10
BA, CA, A10
BA, RA
BA, A10
×
OC, BA
×
×
×
BA, CA, A10
BA, CA, A10
BA, RA
BA, A10
×
OC, BA
Command
DESL
Action
Continue burst to end -
NOP
Continue burst to end -
BST
READ/READA
WRIT/ WRITA
ACT
PRE/PALL
REF
MRS/EMRS
DESL
NOP
BST
READ/READA
WRIT/ WRITA
ACT
PRE/PALL
REF
MRS/EMRS
DESL
NOP
BST
READ/READA
WRIT/WRITA
ACT
PRE/PALL
REF
MRS/EMRS
DESL
NOP
BST
READ/READA
WRIT/WRITA
ACT
PRE/PALL
REF
MRS/EMRS
ILLEGAL
ILLEGAL (2)
ILLEGAL (2)
ILLEGAL (2)
ILLEGAL (2)
ILLEGAL
ILLEGAL
Continue burst to end -Write
recovering with auto precharge
Continue burst to end -Write
recoveringwith auto precharge
ILLEGAL
ILLEGAL(2)
ILLEGAL (2)
ILLEGAL (2)
ILLEGAL (2)
ILLEGAL
ILLEGAL
Nop Enter idle after tRP
Nop Enter idle after tRP
ILLEGAL
ILLEGAL (2)
ILLEGAL (2)
ILLEGAL(2)
Nop Enter idle after tRP
ILLEGAL
ILLEGAL
Nop Enter bank active after tRCD
Nop Enter bank active after tRCD
ILLEGAL
ILLEGAL (2)
ILLEGAL (2)
ILLEGAL (2,8)
ILLEGAL (2)
ILLEGAL
ILLEGAL
Note: H=VIH, L=VIL x= VIH or VIL, V = Valid Data, BA= Bank Address, CA+Column Address, RA=Row Address, OC= Op-Code
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
PRELIMINARYINFORMATION Rev. 00C
01/20/05
11

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