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49LF002 데이터시트 PDF




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부품번호 49LF002 기능
기능 2 Mbit / 3 Mbit / 4 Mbit / 8 Mbit Firmware Hub
제조업체 Silicon Storage Technology Inc
로고 Silicon Storage Technology  Inc 로고


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49LF002 데이터시트, 핀배열, 회로
2 Mbit / 3 Mbit / 4 Mbit / 8 Mbit Firmware Hub
SST49LF002A / SST49LF003A / SST49LF004A / SST49LF008A
SST49LF002A / 003A / 004A / 008A2 Mb / 3 Mb / 4 Mb / 8 Mb Firmware Hub for Intel 8xx Chipsets
FEATURES:
Advance Information
• Firmware Hub for Intel 8xx Chipsets
• 2 Mbit, 3 Mbit, 4 Mbit, or 8 Mbit SuperFlash
memory array for code/data storage
– SST49LF002A: 256K x8 (2 Mbit)
– SST49LF003A: 384K x8 (3 Mbit)
– SST49LF004A: 512K x8 (4 Mbit)
– SST49LF008A: 1024K x8 (8 Mbit)
• Flexible Erase Capability
– Uniform 4 KByte Sectors
– Uniform 16 KByte overlay blocks for
SST49LF002A
– Uniform 64 KByte overlay blocks for
SST49LF003A/004A/008A
– Top Boot Block protection
- 16 KByte for SST49LF002A
- 64 KByte for SST49LF003A/004A/008A
– Chip-Erase for PP Mode Only
• Single 3.0-3.6V Read and Write Operations
• Superior Reliability
– Endurance:100,000 Cycles (typical)
– Greater than 100 years Data Retention
• Low Power Consumption
– Active Read Current: 6 mA (typical)
– Standby Current: 10 µA (typical)
• Fast Sector-Erase/Byte-Program Operation
– Sector-Erase Time: 18 ms (typical)
– Block-Erase Time: 18 ms (typical)
– Chip-Erase Time: 70 ms (typical)
– Byte-Program Time: 14 µs (typical)
– Chip Rewrite Time:
SST49LF002A: 4 seconds (typical)
SST49LF003A: 6 seconds (typical)
SST49LF004A: 8 seconds (typical)
SST49LF008A: 15 seconds (typical)
– Single-pulse Program or Erase
– Internal timing generation
• Two Operational Modes
– Firmware Hub Interface (FWH) Mode for
in-system operation
– Parallel Programming (PP) Mode for fast
production programming
• Firmware Hub Hardware Interface Mode
– 5-signal communication interface supporting
byte Read and Write
– 33 MHz clock frequency operation
– WP# and TBL# pins provide hardware write
protect for entire chip and/or top Boot Block
– Block Locking Register for all blocks
– Standard SDP Command Set
– Data# Polling and Toggle Bit for End-of-Write
detection
– 5 GPI pins for system design flexibility
– 4 ID pins for multi-chip selection
• Parallel Programming (PP) Mode
– 11-pin multiplexed address and
8-pin data I/O interface
– Supports fast In-System or PROM programming
for manufacturing
• CMOS and PCI I/O Compatibility
• Packages Available
– 32-lead PLCC
– 32-lead TSOP (8mm x 14mm)
PRODUCT DESCRIPTION
The SST49LF00xA flash memory devices are designed
to be read-compatible with the Intel 82802 Firmware Hub
(FWH) device for PC-BIOS application. It provides pro-
tection for the storage and update of code and data in
addition to adding system design flexibility through five
general purpose inputs. Two interface modes are sup-
ported by the SST49LF00xA: Firmware Hub (FWH)
Interface Mode for In-System programming and Parallel
Programming (PP) Mode for fast factory programming of
PC-BIOS applications.
The SST49LF00xA flash memory devices are manufac-
tured with SST’s proprietary, high performance Super-
Flash Technology. The split-gate cell design and thick
oxide tunneling injector attain better reliability and manu-
facturability compared with alternate approaches. The
SST49LF00xA devices significantly improve performance
and reliability, while lowering power consumption. The
SST49LF00xA devices write (Program or Erase) with a
single 3.0-3.6V power supply. It uses less energy during
Erase and Program than alternative flash memory tech-
nologies. The total energy consumed is a function of the
applied voltage, current and time of application. Since for
©2001 Silicon Storage Technology, Inc.
S71161-06-000 9/01
504
1
The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc.
MPF is a trademark of Silicon Storage Technology, Inc. Intel is a registered trademark of Intel Corporation.
These specifications are subject to change without notice.




49LF002 pdf, 반도체, 판매, 대치품
2 Mbit / 3 Mbit / 4 Mbit / 8 Mbit Firmware Hub
SST49LF002A / SST49LF003A / SST49LF004A / SST49LF008A
Advance Information
TABLE 2: FWH WRITE CYCLE
Clock
Cycle
1
Field
Name
START
Field Contents
FWH[3:0]1
1110
FWH[3:0]
Direction
IN
2
IDSEL
0000 to 1111
IN
3-9 IMADDR YYYY
IN
10
IMSIZE
0000 (1 byte)
IN
11 DATA YYYY
IN
12 DATA YYYY
IN
13 TAR0
1111
IN then Float
14
TAR1
1111 (float)
Float then OUT
15 RSYNC 0000
OUT
16 TAR0
1111
OUT then Float
17
TAR1
1111 (float)
Float then IN
1. Field contents are valid on the rising edge of the present clock cycle.
Comments
FWH4 must be active (low) for the part to respond.
Only the last start field (before FWH4 transitioning
high) should be recognized. The START field contents
indicate a FWH memory read cycle.
Indicates which SST49LF00xA device should
respond. If the IDSEL (ID select) field matches the
value ID[3:0], then that particular device will respond
to the whole bus cycle.
These seven clock cycles make up the 28-bit memory
address. YYYY is one nibble of the entire address.
Addresses are transferred most-significant nibble first.
This size field indicates how many bytes will be
transferred during multi-byte operations. The FWH
only supports single-byte writes. IMSIZE=0000b
This field is the least-significant nibble of the data byte.
This data is either the data to be programmed into the
flash memory or any valid flash command.
This field is the most-significant nibble of the data byte.
In this clock cycle, the master (Intel ICH) has driven the
then float bus to all ‘1’s and then floats the bus prior to
the next clock cycle. This is the first part of the bus
“turnaround cycle.”
The SST49LF00xA takes control of the bus during this
cycle. During the next clock cycle it will be driving the
“sync” data.
The SST49LF00xA outputs the values 0000, indicat-
ing that it has received data or a flash command.
In this clock cycle, the SST49LF00xA has driven the
bus to all then float ‘1’s and then floats the bus prior to
the next clock cycle. This is the first part of the bus
“turnaround cycle.”
The master (Intel ICH) resumes control of the bus during
this cycle.
T2.4 504
CLK
FWH4
FWH[3:0]
STR IDS
FIGURE 2: WRITE WAVEFORMS
IMADDR
IMS DATA
TAR RSYNC
TAR
504 ILL F60.1
©2001 Silicon Storage Technology, Inc.
4
S71161-06-000 9/01 504

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49LF002 전자부품, 판매, 대치품
2 Mbit / 3 Mbit / 4 Mbit / 8 Mbit Firmware Hub
SST49LF002A / SST49LF003A / SST49LF004A / SST49LF008A
Advance Information
Block Locking Registers
SST49LF00xA provides software controlled lock protection through a set of Block Locking registers. The Block
Locking Registers are read/write registers and it is accessible through standard addressable memory locations
specified in Table 4 and Table 5. Unused register locations will read as 00H.
TABLE 4: BLOCK LOCKING REGISTERS FOR SST49LF002A1
Register
T_BLOCK_LK
T_MINUS01_LK
T_MINUS02_LK
T_MINUS03_LK
T_MINUS04_LK
T_MINUS05_LK
T_MINUS06_LK
T_MINUS07_LK
1. Default value at power up is 01H
Block Size
16K
16K
16K
16K
16K
16K
16K
16K
16K
16K
16K
16K
16K
16K
16K
16K
Protected Memory
Address Package
3FFFFH - 3C000H
3BFFFH - 38000H
37FFFH - 34000H
33FFFH - 30000H
2FFFFH - 2C000H
2BFFFH - 28000H
27FFFH - 24000H
23FFFH - 20000H
1FFFFH - 1C000H
1BFFFH - 18000H
17FFFH - 14000H
13FFFH - 10000H
0FFFFH - 0C000H
0BFFFH - 08000H
07FFFH - 04000H
03FFFH - 00000H
Memory Map
Register Address
FFBF8002H
FFBF0002H
FFBE8002H
FFBE0002H
FFBD8002H
FFBD0002H
FFBC8002H
FFBC0002H
T4.1 504
TABLE 5: BLOCK LOCKING REGISTERS FOR SST49LF003A/004A/008A1
Register
T_BLOCK_LK
T_MINUS01_LK
T_MINUS02_LK
T_MINUS03_LK
T_MINUS04_LK
T_MINUS05_LK
T_MINUS06_LK
T_MINUS07_LK
T_MINUS08_LK
T_MINUS09_LK
T_MINUS10_LK
T_MINUS11_LK
T_MINUS12_LK
T_MINUS13_LK
T_MINUS14_LK
T_MINUS15_LK
Block
Size
64K
64K
64K
64K
64K
64K
64K
64K
64K
64K
64K
64K
64K
64K
64K
64K
Protected Memory Address Range
SST49LF003A
SST49LF004A
SST49LF008A
07FFFFH - 070000H 07FFFFH - 070000H 0FFFFFH - 0F0000H
06FFFFH - 060000H 06FFFFH - 060000H 0EFFFFH - 0E0000H
05FFFFH - 050000H 05FFFFH - 050000H 0DFFFFH - 0D0000H
04FFFFH - 040000H 04FFFFH - 040000H 0CFFFFH - 0C0000H
03FFFFH - 030000H 03FFFFH - 030000H 0BFFFFH - 0B0000H
02FFFFH - 020000H 02FFFFH - 020000H 0AFFFFH - 0A0000H
01FFFFH - 010000H 09FFFFH - 090000H
00FFFFH - 000000H 08FFFFH - 080000H
07FFFFH - 070000H
06FFFFH - 060000H
05FFFFH - 050000H
04FFFFH - 040000H
03FFFFH - 030000H
02FFFFH - 020000H
01FFFFH -010000H
00FFFFH - 000000H
1. Default value at power up is 01H
Memory Map
Register Address
FFBF0002H
FFBE0002H
FFBD0002H
FFBC0002H
FFBB0002H
FFBA0002H
FFB90002H
FFB80002H
FFB70002H
FFB60002H
FFB50002H
FFB40002H
FFB30002H
FFB20002H
FFB10002H
FFB00002H
T5.2 504
©2001 Silicon Storage Technology, Inc.
7
S71161-06-000 9/01 504

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부품번호상세설명 및 기능제조사
49LF002

2 Mbit / 3 Mbit / 4 Mbit / 8 Mbit Firmware Hub

Silicon Storage Technology  Inc
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