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5241 데이터시트 PDF




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부품번호 5241 기능
기능 Quad Digitally Programmable Potentiometers (DPP) with 64 Taps and 2-wire Interface
제조업체 Catalyst Semiconductor
로고 Catalyst Semiconductor 로고


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5241 데이터시트, 핀배열, 회로
CAT5241
ALOGEN FR
Quad Digitally Programmable Potentiometers (DPP™)
with 64 Taps and 2-wire Interface
FEATURES
LEA D F REETM
s Four linear-taper digitally programmable
potentiometers
s 64 resistor taps per potentiometer
s End to end resistance 2.5k, 10k, 50kor 100k
s Potentiometer control and memory access via
2-wire interface (I2C like)
s Low wiper resistance, typically 80
s Nonvolatile memory storage for up to four wiper
settings for each potentiometer
s Automatic recall of saved wiper settings at
power up
s 2.5 to 6.0 volt operation
s Standby current less than 1µA
s 1,000,000 nonvolatile WRITE cycles
s 100 year nonvolatile memory data retention
s 20-lead SOIC and TSSOP packages
s Industrial temperature range
DESCRIPTION
The CAT5241 is four Digitally Programmable
Potentiometers (DPPs™) integrated with control logic
and 16 bytes of NVRAM memory. Each DPP consists of
a series of 63 resistive elements connected between two
externally accessible end points. The tap points between
each resistive element are connected to the wiper outputs
with CMOS switches. A separate 6-bit control register
(WCR) independently controls the wiper tap switches for
each DPP. Associated with each wiper control register
are four 6-bit non-volatile memory data registers (DR)
used for storing up to four wiper settings. Writing to the
wiper control register or any of the non-volatile data
registers is via a 2-wire serial bus (I2C-like). On power-
up, the contents of the first data register (DR0) for each
of the four potentiometers is automatically loaded into its
respective wiper control register (WCR).
The CAT5241 can be used as a potentiometer or as a
two terminal, variable resistor. It is intended for circuit
level or system level adjustments in a wide variety of
applications.
PIN CONFIGURATION
FUNCTIONAL DIAGRAM
SOIC Package (J, W)
TSSOP Package (U, Y)
RW0
RL0
RH0
A0
A2
RW1
RL1
RH1
SDA
GND
1 20
2 19
3 18
4 17
5 CAT 16
6 5241 15
7 14
8 13
9 12
10 11
VCC
RW3
RL3
RH3
A1
A3
SCL
RW2
RL2
RH2
RH0 RH1 RH2 RH3
SCL
SDA
2-WIRE BUS
INTERFACE
WIPER
CONTROL
REGISTERS
A0
A1 CONTROL
A2 LOGIC
A3
NONVOLATILE
DATA
REGISTERS
RL0 RL1 RL2 RL3
R W0
R W1
R W2
R W3
© 2004 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
1
Document No. 2011, Rev. J




5241 pdf, 반도체, 판매, 대치품
CAT5241
D.C. OPERATING CHARACTERISTICS
Over recommended operating conditions unless otherwise stated.
Symbol
ICC
ISB
ILI
ILO
VIL
VIH
VOL1
Parameter
Test Conditions
Min
Power Supply Current
fSCL = 400kHz
Standby Current (VCC = 5.0V) VIN = GND or VCC; SDA Open
Input Leakage Current
VIN = GND to VCC
Output Leakage Current
VOUT = GND to VCC
Input Low Voltage
-1
Input High Voltage
VCC x 0.7
Output Low Voltage (VCC = 3.0V)
IOL = 3 mA
Typ Max Units
1 mA
1 µA
10 µA
10 µA
VCC x 0.3 V
VCC + 1.0 V
0.4 V
CAPACITANCE
TA = 25°C, f = 1.0 MHz, VCC = 5V
Symbol Test
CI/O(1) Input/Output Capacitance (SDA)
CIN(1) Input Capacitance (A0, A1, A2, A3, SCL)
Conditions Min Typ
Max Units
VI/O = 0V
8 pF
VIN = 0V
6 pF
A.C. CHARACTERISTICS
Over recommended operating conditions unless otherwise stated.
Symbol Parameter
fSCL Clock Frequency
TI(1) Noise Suppression Time Constant at SCL, SDA Inputs
tAA
tBUF(1)
SLC Low to SDA Data Out and ACK Out
Time the Bus Must be Free Before a New
Transmission Can Start
tHD:STA Start Condition Hold Time
tLOW
Clock Low Period
tHIGH
Clock High Period
tSU:STA Start Condition SetupTime (For a Repeated Start Condition)
tHD:DAT Data in Hold Time
tSU:DAT
tR(1)
tF(1)
Data in Setup Time
SDA and SCL Rise Time
SDA and SCL Fall Time
tSU:STO Stop Condition Setup Time
tDH Data Out Hold Time
Min Typ
1.2
0.6
1.2
0.6
0.6
0
100
0.6
50
Max
400
50
0.9
Units
kHz
ns
µs
µs
µs
µs
µs
µs
ns
ns
0.3 µs
300 ns
µs
ns
POWER UP TIMING (1)
Over recommended operating conditions unless otherwise stated.
Symbol Parameter
Min
tPUR Power-up to Read Operation
tPUW Power-up to Write Operation
Note:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
Typ
Max
1
1
Units
ms
ms
Document No. 2011, Rev. J
4

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5241 전자부품, 판매, 대치품
CAT5241
WRITE OPERATIONS
In the Write mode, the Master device sends the START
condition and the slave address information to the Slave
device. After the Slave generates an acknowledge, the
Master sends the instruction byte that defines the
requested operation of CAT5241. The instruction byte
consist of a four-bit opcode followed by two register
selection bits and two pot selection bits. After receiving
another acknowledge from the Slave, the Master device
transmits the data to be written into the selected register.
The CAT5241 acknowledges once more and the Master
generates the STOP condition, at which time if a non-
volatile data register is being selected, the device begins
an internal programming cycle to non-volatile memory.
While this internal cycle is in progress, the device will not
respond to any request from the Master device.
Acknowledge Polling
The disabling of the inputs can be used to take advantage
of the typical write cycle time. Once the stop condition is
issued to indicate the end of the host's write operation,
the CAT5241 initiates the internal write cycle. ACK
polling can be initiated immediately. This involves issuing
the start condition followed by the slave address. If the
CAT5241 is still busy with the write operation, no ACK
will be returned. If the CAT5241 has completed the write
operation, an ACK will be returned and the host can then
proceed with the next instruction operation.
Figure 5. Slave Address Bits
CAT5241 0 1 0 1 A3 A2 A1 A0
* A0, A1, A2 and A3 correspond to pin A0, A1, A2 and A3 of the device.
** A0, A1, A2 and A3 must compare to its corresponding hard wired input pins.
Figure 6. Write Timing
BUS ACTIVITY:
MASTER
S
T
A
R
T
SLAVE/DPP
ADDRESS
Fixed
Variable
INSTRUCTION
BYTE
op code
DR WCR DATAPot/WCR Data Register
Address Address
S
T
O
P
SDA LINE S
P
A AA
C CC
K KK
7 Document No. 2011, Rev. J

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