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54175 데이터시트 PDF




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부품번호 54175 기능
기능 Hex/Quad D Flip-Flops with Clear
제조업체 National Semiconductor
로고 National Semiconductor 로고


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54175 데이터시트, 핀배열, 회로
June 1989
54174 DM54174 DM74174 54175 DM54175 DM74175
Hex Quad D Flip-Flops with Clear
General Description
These positive-edge triggered flip-flops utilize TTL circuitry
to implement D-type flip-flop logic All have a direct clear
input and the quad (175) version features complementary
outputs from each flip-flop
Information at the D inputs meeting the setup and hold time
requirements is transferred to the Q outputs on the positive-
going edge of the clock pulse Clock triggering occurs at a
particular voltage level and is not directly related to the tran-
sition time of the positive-going pulse When the clock input
is at either the high or low level the D input signal has no
effect at the output
Features
Y 174 contains six flip-flops with single-rail outputs
Y 175 contains four flip-flops with double-rail outputs
Y Buffered clock and direct clear inputs
Y Individual data input to each flip-flop
Y Applications include
Buffer storage registers
Shift registers
Pattern generators
Y Typical clock frequency 40 MHz
Y Typical power dissipation per flip-flop 38 mW
Y Alternate Military Aerospace device (54174 54175) is
available Contact a National Semiconductor Sales Of-
fice Distributor for specifications
Connection Diagrams
Dual-In-Line Package
Dual-In-Line Package
TL F 6557 – 1
Order Number 54174DMQB 54174FMQB DM54174J
DM54174W or DM74174N
See NS Package Number J16A N16E or W16A
TL F 6557 – 2
Order Number 54175DMQB 54175FMQB DM54175J
DM54175W or DM74175N
See NS Package Number J16A N16E or W16A
Function Table (Each Flip-Flop)
C1995 National Semiconductor Corporation
Inputs
Outputs
Clear
Clock
D
Q
Q
L X XL H
H
u HH
L
H
u LL
H
H
L
X Q0
Q0
H e High Level (steady state)
L e Low Level (steady state)
X e Don’t Care
u e Transition from low to high level
Q0 e The level of Q before the indicated steady-state input conditions were established
e 175 only
TL F 6557
RRD-B30M105 Printed in U S A




54175 pdf, 반도체, 판매, 대치품
’175 Electrical Characteristics
over recommended operating free air temperature range (unless otherwise noted)
Symbol
VI
VOH
VOL
II
IIH
IIL
IOS
ICC
Parameter
Input Clamp Voltage
High Level Output
Voltage
Low Level Output
Voltage
Input Current Max
Input Voltage
High Level Input Current
Low Level Input Current
Short Circuit
Output Current
Supply Current
Conditions
VCC e Min II e b12 mA
VCC e Min IOH e Max
VIL e Max VIH e Min
VCC e Min IOL e Max
VIH e Min VIL e Max
VCC e Max VI e 5 5V
VCC e Max VI e 2 4V
VCC e Max VI e 0 4V
VCC e Max
(Note 2)
VCC e Max (Note 3)
DM54
DM74
Min
24
b20
b18
Typ
(Note 1)
30
Max
b1 5
04
1
40
b1 6
b57
b57
45
Units
V
V
V
mA
mA
mA
mA
mA
’175 Switching Characteristics
at VCC e 5V and TA e 25 C (See Section 1 for Test Waveforms and Output Load)
Symbol
Parameter
From (Input)
To (Output)
RL e 400X CL e 15 pF
Min Max
Units
fMAX
Maximum Clock
Frequency
30 MHz
tPLH Propagation Delay Time Clock to
Low to High Level Output
Any Q or Q
25 ns
tPHL Propagation Delay Time Clock to
High to Low Level Output
Any Q or Q
25 ns
tPLH Propagation Delay Time Clear to
Low to High Level Output
Any Q
25 ns
tPHL Propagation Delay Time Clear to
High to Low Level Output
Any Q
40 ns
Note 1 All typicals are at VCC e 5V TA e 25 C
Note 2 Not more than one output should be shorted at a time
Note 3 With all outputs open and 4 5V applied to all DATA and CLEAR inputs ICC is measured after a momentary ground then 4 5V applied to the CLOCK
4

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54175 전자부품, 판매, 대치품
Physical Dimensions inches (millimeters)
16-Lead Ceramic Dual-In-Line Package (J)
Order Number 54174DMQB 54175DMQB DM54174J or DM54175J
NS Package Number J16A
16-Lead Molded Dual-In-Line Package (N)
Order Number DM74174N or DM74175N
NS Package Number N16E
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