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54ABT16500 데이터시트 PDF




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부품번호 54ABT16500 기능
기능 18-Bit Universal Bus Transceivers with TRI-STATE Outputs
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54ABT16500 데이터시트, 핀배열, 회로
July 1998
54ABT16500
18-Bit Universal Bus Transceivers with TRI-STATE®
Outputs
General Description
These 18-bit universal bus transceivers combine D-type
latches and D-type flip-flops to allow data flow in transparent,
latched, and clocked modes.
Data flow in each direction is controlled by output-enable
(OEAB and OEBA), latch-enable (LEAB and LEBA), and
clock (CLKAB and CLKBA) inputs. For A-to-B data flow, the
device operates in the transparent mode when LEAB is high.
When LEAB is low, the A data is latched if CLKAB is held at
a high or low logic level. If LEAB is low, the A bus data is
stored in the latch/flip-flop on the high-to-low transition of
CLKAB. Output-enable OEAB is active-high. When OEAB is
high, the outputs are active. When OEAB is low, the outputs
are in the high-impedance state.
Data flow for B to A is similar to that of A to B but uses OEBA,
LEBA, and CLKBA. The output enables are complementary
(OEAB is active high and OEBA is active low).
To ensure the high-impedance state during power up or
power down, OE should be tied to GND through a pulldown
resistor; the minimum value of the resistor is determined by
the current-sourcing capability of the driver.
Features
n Combines D-Type latches and D-Type flip-flops for
operation in transparent, latched, or clocked mode
n Flow-through architecture optimizes PCB layout
n Guaranteed latch-up protection
n High impedance glitch free bus loading during entire
power up and power down cycle
n Non-destructive hot insertion capability
n Standard Microcircuit Drawing (SMD) 5962-9687001
Ordering Code
Military
54ABT16500W-QML
Package
Number
WA56A
56-Lead Cerpack
Package Description
TRI-STATE® is a registered trademark of National Semiconductor Corporation.
© 1998 National Semiconductor Corporation DS100225
PrintDate=1998/07/14 PrintTime=11:08:55 43605 ds100225 Rev. No. 1 cmserv Proof
www.national.com
1
1




54ABT16500 pdf, 반도체, 판매, 대치품
Absolute Maximum Ratings (Note 4)
Storage Temperature
Ambient Temperature under Bias
Junction Temperature under Bias
Ceramic
VCC Pin Potential to
Ground Pin
Input Voltage (Note 4)
Input Current (Note 4)
Voltage Applied to Any Output
in the Disabled or
Power-off State
in the HIGH State
Current Applied to Output
in LOW State (Max)
DC Latchup Source Current
−65˚C to +150˚C
−55˚C to +125˚C
−55˚C to +175˚C
−0.5V to +7.0V
−0.5V to +7.0V
−30 mA to +5.0 mA
−0.5V to 5.5V
−0.5V to VCC
twice the rated IOL (mA)
−500 mA
Over Voltage Latchup (I/O)
10V
Recommended Operating
Conditions
Free Air Ambient Temperature
Military
−55˚C to +125˚C
Supply Voltage
Military
+4.5V to +5.5V
Minimum Input Edge Rate
(V/t)
Data Input
50 mV/ns
Enable Input
20 mV/ns
Note 4: Absolute maximum ratings are values beyond which the device may
be damaged or have its useful life impaired. Functional operation under these
conditions is not implied.
Note 5: Either voltage limit or current limit is sufficient to protect inputs.
DC Electrical Characteristics
Symbol
Parameter
VIH Input HIGH Voltage
VIL Input LOW Voltage
VCD Input Clamp Diode Voltage
VOH Output HIGH Voltage
VOL Output LOW Voltage
IIH Input HIGH Current
54ABT
54ABT
54ABT
IBVI Input HIGH Current Breakdown Test
IIL Input LOW Current
VID Input Leakage Test
ABT16500
Min Typ Max
2.0
0.8
−1.2
2.5
2.0
0.55
5
5
7
−5
−5
4.75
Units
V
V
V
V
V
V
µA
µA
µA
V
IIH +
IOZH
IIL +
IOZL
IOS
ICEX
IZZ
ICCH
ICCL
ICCZ
Output Leakage Current
Output Leakage Current
Output Short-Circuit Current
Output High Leakage Current
Bus Drainage Test
Power Supply Current
Power Supply Current
Power Supply Current
−100
50 µA
−50 µA
−275
50
100
1.0
68
1.0
mA
µA
µA
mA
µA
mA
ICCT Additional ICC/Input
2.5 mA
ICCD
Dynamic ICC
(Note 6)
No Load
mA/
0.23 MHz
Note 6: Guaranteed, but not tested.
VCC
Min
Min
Min
Min
Max
Max
Max
0.0
0 − 5.5V
0 − 5.5V
Max
Max
0.0
Max
Max
Max
Max
Max
Conditions
Recognized HIGH Signal
Recognized LOW Signal
IIN = −18 mA
IOH = −3 mA
IOH = −24 mA
IOL = 48 mA
VIN = 2.7V (Note 6)
VIN = VCC
VIN = 7.0V
VIN = 0.5V (Note 6)
VIN = 0.0V
IID = 1.9 µA
All Other Pins Grounded
VOUT = 2.7V; OE, OE = 2.0V
VOUT = 0.5V; OE, OE = 2.0V
VOUT = 0V
VOUT = VCC
VOUT = 5.5V; All Others GND
All Outputs HIGH
An or Bn Outputs Low
OEn = VCC,
All Others at VCC or GND
VI = VCC − 2.1V
All Others at VCC or GND
Outputs Open
Transparent Mode
One Bit Toggling, 50% Duty Cycle
www.national.com
4
PrintDate=1998/07/14 PrintTime=11:08:55 43605 ds100225 Rev. No. 1 cmserv Proof
4

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54ABT16500 전자부품, 판매, 대치품
AC Loading
DS100225-3
*Includes jig and probe capacitance.
FIGURE 1. Standard AC Test Load
DS100225-4
FIGURE 5. Propagation Delay,
Pulse Width Waveforms
FIGURE 2. VM = 1.5V
DS100225-5
Input Pulse Requirements
Amplitude Rep. Rate
tW
3.0V
1 MHz 500 ns
tr
2.5 ns
tf
2.5 ns
FIGURE 3. Test Input Signal Requirements
DS100225-6
FIGURE 6. TRI-STATE Output HIGH
and LOW Enable and Disable Times
DS100225-7
FIGURE 4. Propagation Delay Waveforms
for Inverting and Non-Inverting Functions
FIGURE 7. Setup Time, Hold Time
and Recovery Time Waveforms
DS100225-8
7
PrintDate=1998/07/14 PrintTime=11:08:56 43605 ds100225 Rev. No. 1 cmserv Proof
www.national.com
7

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