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Número de pieza | HY62UF16101CSLF | |
Descripción | 64Kx16bit full CMOS SRAM | |
Fabricantes | Hynix Semiconductor | |
Logotipo | ||
Hay una vista previa y un enlace de descarga de HY62UF16101CSLF (archivo pdf) en la parte inferior de esta página. Total 10 Páginas | ||
No Preview Available ! HY62UF16101C Series
64Kx16bit full CMOS SRAM
Document Title
64K x16 bit 3.0V Super Low Power Full CMOS Slow SRAM
Revision History
Revision No History
03 Divide output load into two factors
- tCLZ,tOLZ,tBLZ,tCHZ,tOHZ,tBHZ,tWHZ,tOW
- Others
Add marking information
04 Add 100ns speed
Draft Date
Remark
Dec.10. 2000 Final
Dec.27. 2000 Final
This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any
responsibility for use of circuits described. No patent licenses are implied.
Rev.04 /Dec. 00
Hynix Semiconductor
1 page HY62UF16101C Series
AC CHARACTERISTICS
Vcc = 2.7~3.3V, TA = 0°C to 70°C / -40°C to 85°C (I), unless otherwise specified
# Symbol
Parameter
-55 -70 -85
Min Max Min Max Min Max
READ CYCLE
1 tRC Read Cycle Time
55 - 70 - 85 -
2 tAA
Address Access Time
- 55 - 70 - 85
3 tACS Chip Select Access Time
- 55 - 70 - 85
4 tOE Output Enable to Output Valid
- 35 - 40 - 45
5 tBA
/LB, /UB Access Time
- 55 - 70 - 85
6 tCLZ Chip Select to Output in Low Z
10 - 10 - 10 -
7 tOLZ Output Enable to Output in Low Z
5-5-5-
8 tBLZ /LB, /UB Enable to Output in Low Z
5-5-5-
9 tCHZ Chip Deselection to Output in High Z 0 30 0 30 0 30
10 tOHZ Out Disable to Output in High Z
0 30 0 30 0 30
11 tBHZ /LB, /UB Disable to Output in High Z 0 30 0 30 0 30
12 tOH
Output Hold from Address Change
10 - 10 - 10 -
WRITE CYCLE
13 tWC Write Cycle Time
55 - 70 - 85 -
14 tCW Chip Selection to End of Write
50 - 60 - 70 -
15 tAW Address Valid to End of Write
50 - 60 - 70 -
16 tBW /LB, /UB Valid to End of Write
50 - 60 - 70 -
17 tAS
Address Set-up Time
0-0-0-
18 tWP Write Pulse Width
45 - 50 - 55 -
19 tWR Write Recovery Time
0-0-0-
20 tWHZ Write to Output in High Z
0 20 0 25 0 30
21 tDW Data to Write Time Overlap
25 - 30 - 35 -
22 tDH Data Hold from Write Time
0-0-0-
23 tOW Output Active from End of Write
5-5-5-
-10
Min Max
100 -
- 100
- 100
- 50
- 100
20 -
5-
10 -
0 30
0 30
0 30
15 -
100 -
80 -
80 -
80 -
0-
75 -
0-
0 35
45 -
0-
10 -
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
AC TEST CONDITIONS
TA = 0°C to 70°C / -40°C to 85°C (I), unless otherwise specified
Parameter
Input Pulse Level
Input Rise and Fall Time
Input and Output Timing Reference Level
Output Load tCLZ,tOLZ,tBLZ,tCHZ,tOHZ,tBHZ,tWHZ,tOW
Others
Value
0.4V to 2.2V
5ns
1.5V
CL = 5pF + 1TTL Load
CL = 30pF + 1TTL Load
AC TEST LOADS
VTM=2.8V
DOUT
1029 Ohm
CL(1)
1728 Ohm
Note
1. Including jig and scope capacitance
Rev.04 /Dec. 00
4
5 Page |
Páginas | Total 10 Páginas | |
PDF Descargar | [ Datasheet HY62UF16101CSLF.PDF ] |
Número de pieza | Descripción | Fabricantes |
HY62UF16101CSLF | 64Kx16bit full CMOS SRAM | Hynix Semiconductor |
HY62UF16101CSLF-I | 64Kx16bit full CMOS SRAM | Hynix Semiconductor |
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