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EL5285CS PDF 데이터시트 : 부품 기능 및 핀배열

부품번호 EL5285CS
기능 Dual and Window 4ns High-Speed Comparators
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EL5285CS 데이터시트, 핀배열, 회로
EL5285C - Preliminary
Dual and Window 4ns High-Speed Comparators
Features
• 4ns typ. propagation delay
• 5V to 12V input supply
• +2.7V to +5V output supply
• True-to-ground input
• Rail-to-rail outputs
• Separate analog and digital
supplies
• Active low latch
• Single available (EL5185C)
• Quad available (EL5485C &
EL5486C)
• Pin-compatible 6ns family
available (EL5x81C, EL5283C &
EL5482C)
Applications
• Threshold detection
• High speed sampling circuits
• High speed triggers
• Line receivers
• PWM circuits
• High speed V/F converters
General Description
The EL5285C comparator is designed for operation in single supply
and dual supply applications with 5V to 12V between VS+ and VS-.
For single supplies, the inputs can operate from 0.1V below ground for
use in ground sensing applications.
The output side of the comparators can be supplied from a single sup-
ply of 2.7V to 5V. The rail-to-rail output swing enables direct
connection of the comparator to both CMOS and TTL logic circuits.
The latch input of the EL5285C can be used to hold the comparator
output value by applying a low logic level to the pin. The EL5285C
features two separate comparators
The EL5285C is available in the 14-pin SO package and is specified
for operation over the full -40°C to +85°C temperature range. Also
available are a single (EL5185C) and quad versions (EL5485C and
EL5486C.)
Pin Configurations
Ordering Information
Part No.
EL5285CS
EL5285CS-T7
EL5285CS-T13
Package
14-Pin SOIC
14-Pin SOIC
14-Pin SOIC
Tape & Reel
-
7”
13”
Outline #
MDP0027
MDP0027
MDP0027
VS+ 1
INA+ 2
INA- 3
NC 4
INB- 5
INB+ 6
VS- 7
+
-
+
-
EL5285C
(14-Pin SO)
14 VSD
13 OUTA
12 LATCHA
11 NC
10 LATCHB
9 OUTB
8 GND
Note: All information contained in this data sheet has been carefully checked and is believed to be accurate as of the date of publication; however, this data sheet cannot be a “controlled document”. Current revisions, if any, to these
specifications are maintained at the factory and are available upon your request. We recommend checking the revision level before finalization of your design documentation.
© 2001 Elantec Semiconductor, Inc.




EL5285CS pdf, 반도체, 판매, 대치품
EL5285C - Preliminary
Dual and Window 4ns High-Speed Comparators
Typical Performance Curves
Propagation Delay vs Overdrive
VIN=5VSTEP
7.8
7.6
TPD-
7.4
7.2
TPD+
7
6.8
6.6
6.4
0.2
0.6
1 1.4 1.8
VOD (V)
VS=±5V
VSD=5V
RL=2.2k
2.2 2.6
Propagation Delay vs Supply Voltage
6.8
VSD=VS+
6.6
VOD=50mV
RL=2.2k
6.4
6.2
TPD-
6
5.8 TPD+
5.6
4 4.2 4.4 4.6 4.8 5 5.2 5.4 5.6 5.8 6
±VS (V)
Propagation Delay vs Overdrive
VIN=1VSTEP
6.1
6
5.9
VS=±5V
VSD=5V
RL=2.2k
5.8 TPD-
5.7
5.6
5.5
5.4 TPD+
5.3
5.2
50 100 150 200 250 300 350 400 450 500 550 600
VOD (mV)
Propagation Delay vs Source Resistance
VIN=1VSTEP
15
VS=±5V
VSD=5V
13 VOD=50mV
RL=2.2k
11
TPD-
9
TPD+
7
5
0 0.4 0.8 1.2 1.6 2
Source Resistance (k)
Digital Supply Current vs Switching Frequency
(per comparator)
25
VS=±5V
TA=25°C
20
15 VSD=5V
10 VSD=3V
5
0
0 10 20 30 40 50
Frequency (MHz)
Propagation Delay vs Overdrive
VIN=3VSTEP
8
7.5
7 TPD-
VS=±5V
VSD=5V
RL=2.2k
6.5
TPD+
6
5.5
5
0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8
VOD (mV)
2
4

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EL5285CS 전자부품, 판매, 대치품
EL5285C - Preliminary
Dual and Window 4ns High-Speed Comparators
Timing Diagram
Latch
Enable
Input
Latch
Differential
Input
Voltage
VIN
Comparator
Output
Compare
ts th
VOD
tpd-
Latch
Compare
tpw(D)
Latch
1.4V
VOS
td+
2.4V
Definition of Terms
Term
VOS
VIN
VOD
tpd+
tpd-
td+
td-
ts
th
tpw (D)
Definition
Input Offset Voltage - Voltage applied between the two input terminals to obtain CMOS logic threshold at the output
Input Voltage Pulse Amplitude - Usually set to 1V for comparator specifications
Input Voltage Overdrive - Usually set to 50mV and in opposite polarity to VIN for comparator specifications
Input to Output High Delay - The propagation delay measured from the time the input signal crosses the input offset voltage to the CMOS
logic threshold of an output low to high transition
Input to Output Low Delay - The propagation delay measured from the time the input signal crosses the input offset voltage to the CMOS
logic threshold of an output high to low transition
Latch Disable to Output High Delay - The propagation delay measured from the latch signal crossing the CMOS threshold in a low to high
transition to the point of the output crossing CMOS threshold in a low to high transition
Latch Disable to Output Low Delay - The propagation delay measured from the latch signal crossing the CMOS threshold in a low to high
transition to the point of the output crossing CMOS threshold in a high to low transition
Minimum Setup Time - The minimum time before the negative transition of the latch signal that an input signal change must be present in
order to be acquired and held at the outputs
Minimum Hold Time - The minimum time after the negative transition of the latch signal that an input signal must remain unchanged in
order to be acquired and held at the output
Minimum Latch Disable Pulse Width - The minimum time that the latch signal must remain high in order to acquire and hold an input signal
change
7

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부품번호상세설명 및 기능제조사
EL5285C

Dual and Window 4ns High-Speed Comparators

Elantec Semiconductor
Elantec Semiconductor
EL5285CS

Dual and Window 4ns High-Speed Comparators

Elantec Semiconductor
Elantec Semiconductor

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