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EM19100M PDF 데이터시트 : 부품 기능 및 핀배열

부품번호 EM19100M
기능 8-BIT 20 MSPS VIDEO A/D CONVERTER (CMOS)
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EM19100M 데이터시트, 핀배열, 회로
EMEM1911910000
8-BIT 20 MS8-PBSITV20IDMESPOS AVI/DDECO OA/NDVCOENRVTEERRTE(RC(MCMOOSS))
GENERAL DESCRIPTION
EM19100 is an 8-bit CMOS A/D converter for video use. The adoption of a 2-step parallel system achieves low
consumption at a maximum conversion speed of 20 MSPS typical.
FEATURES
• 20MSPS maximum conversion speed
• Build-in sampling and hold circuit
• Internal self-bias reference voltage
• 90mW power dissipation at 20MSPS
• +5V single power supply
• Available in 24 pin SOP
• Series
EM19100M for 300 mil SOP
EM19100S for 209 mil SOP
APPLICATION
TV,VCR digital systems and a wide range of fields where high speed A/D conversion is required.
PIN ASSIGNMENT
FUNCTIONAL BLOCK DIAGRAM
EM19100
OE
DVSS
D0
D1
D2
D3
D4
D5
D6
D7
DVDD
CLK
1
2
3
4
5
6
7
8
9
10
11
12
24 DVSS
23 VRB
22 VRBS
21 AVSS
20 AVSS
19 VIN
18 AVDD
17 VRT
16 VRTS
15 AVDD
14 AVDD
13 DVDD
/OE 1
DVSS 2
D0 3
D1 4
D2 5
D3 6
D4 7
D5 8
D6 9
D7 10
DVDD 11
CLK 12
Lower data
latches
Upper data
latches
Lower encoder
(4bit)
Lower encoder
(4bit)
Upper encoder
(4bit)
Clock generator
Reference voltage
Lower
Comparators with
S/ H (4bit)
Lower
Comparators with
S/ H (4bit)
Upper
Comparators with
S/ H (4bit)
24 DVSS
23 VRB
22 VRBS
21 AVSS
20 AVSS
19 VIN
18 AVDD
17 VRT
16 VRTS
15 AVDD
14 AVDD
13 DVDD
* This specification are subject to be changed without notice.
1.26.1996 1




EM19100M pdf, 반도체, 판매, 대치품
EM19100
8-BIT 20 MSPS VIDEO A/D CONVERTER (CMOS)
Timing explanation
EM19100 is a 2-step parallel system A/D converter featuring a 4-bit upper comparators group and 2 lower
comparators groups of 4-bit each. The reference voltage that is equal to the voltage between VRT-VRB/16 is
constantly applied to the upper 4-bit comparator block. Voltage that corresponded to the upper data is fed through
the reference supply to the lower data. VRTS and VRBS pins serve for the self generation of VRT (Reference
voltage top) and V (Reference voltage bottom).
RB
This IC uses an offset cancel type comparator and operates synchronously with an external clock. It features the
following operating modes which are respectively indicated on the timing chart with S, H, C symbols. That is
input sampling (auto zero) mode, input hold mode and comparison mode.
The operation of respective parts is as indicated in the chart. For instance input voltage Vi(1) is sampled with the
falling edge of the first clock by means of the upper comparator block and the lower comparator A block. The
upper comparators block finalizes comparison data MD(1) with the rising edge of the first clock. Simultaneously
the reference supply generates the lower reference voltage RV(1) that corresponded to the upper results. The
lower comparator block finalizes comparison data LD(1) with the rising edge of the second clock. MD(1) and
LD(1) are combined and output as Out(1) with the rising edge the 3rd clock. Accordingly there is a 2.5 clock delay
from the analog input sampling point to the digital data output.
Application Note
VDD,VSS
To reduce noise effects, separate the analog and digital systems close to the device. For both the digital and
analog VDD pins, use a ceramic capacitor of about 0.1uF set as close as possible to the pin to bypass to the
respective GND’s.
Analog input
Compared with the flash type A/D converter, the input capacitance of the analog input is rather small. However
it is necessary to conduct the drive with an amplifier featuring sufficient band and drive capability. When
driving with an amplifier of low output impedance, parasite oscillation may occur. That may be prevented by
inserting a resistance of about 100in series between the amplifier output and A/D input.
Clock input
The clock line wiring should be as short as possible also, to avoid any interference with other signals, separate
it from other circuits
Reference input
Voltage between VRT to VRB is compatible with the dynamic range of the analog input. Bypassing VRT and
V
RB
pins
to
GND,
by
means
of
a
capacitor
about
0.1µF,
stable
characteristics
are
obtained.
By
shorting
V
RT
and VRTS, VRB and VRBS, the self bias function that generates VRT=2.6V and VRB=0.6V, is activated.
Timing
Analog input is sampled with the falling edge of CLK and output as digital data with a delay of 2.5 clocks and
* This specification are subject to be changed without notice.
1.26.1996 4

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부품번호상세설명 및 기능제조사
EM19100

8-BIT 20 MSPS VIDEO A/D CONVERTER (CMOS)

ELAN Microelectronics Corp
ELAN Microelectronics Corp
EM19100M

8-BIT 20 MSPS VIDEO A/D CONVERTER (CMOS)

ELAN Microelectronics Corp
ELAN Microelectronics Corp

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