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EM19101 PDF 데이터시트 : 부품 기능 및 핀배열

부품번호 EM19101
기능 8-BIT 5 MSPS A/D CONVERTER (CMOS)
제조업체 ELAN Microelectronics Corp
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EM19101 데이터시트, 핀배열, 회로
EMEM1911910011
8-BIT 5 M8S-BPIST 5AM/DSPCS OA/NDVCOENRVTEERRTE(RC(MCMOOSS))
GENERAL DESCRIPTION
EM19101 is a 8-bit CMOS A/D converter for scanner use. The adoption of a 2-step parallel system achieves low
consumption at a maximum conversion speed of 7 MSPS.
FEATURES
• 7MSPS maximum conversion speed
• Build-in sampling and hold circuit
• Internal self-bias reference voltage
• 45 mW very low power dissipation at 5MSPS
• +5V single power supply
• Available in 24 pin SOP
• Series
EM19101M for 300 mil SOP
EM19101S for 209 mil SOP
APPLICATION
Scanner and a wide range of fields where high speed A/D conversion is required in the digital communication.
PIN ASSIGNMENT
EM19101
OE
DVSS
D0
D1
D2
D3
D4
D5
D6
D7
DVDD
CLK
1
2
3
4
5
6
7
8
9
10
11
12
24 DVSS
23 VRB
22 VRBS
21 AVSS
20 AVSS
19 VIN
18 AVDD
17 VRT
16 VRTS
15 AVDD
14 AVDD
13 DVDD
FUNCTIONAL BLOCK DIAGRAM
/OE 1
DVSS 2
D0 3
D1 4
D2 5
D3 6
D4 7
D5 8
D6 9
D7 10
DVDD 11
CLK 12
Lower data
latches
Lower encoder
(4bit)
Upper data
latches
Upper encoder
(4bit)
Clock generator
Reference voltage
Lower
Comparators with
S/ H (4bit)
Upper
Comparators with
S/ H (4bit)
24 DVSS
23 VRB
22 VRBS
21 AVSS
20 AVSS
19 VIN
18 AVDD
17 VRT
16 VRTS
15 AVDD
14 AVDD
13 DVDD
* This specification are subject to be changed without notice.
4.23.1997 1




EM19101 pdf, 반도체, 판매, 대치품
EM19101
8-BIT 5 MSPS A/D CONVERTER (CMOS)
Parameter
Digital output current
Digital output current
Output data delay
Integral nonlinearity
Differential nonlinearity
Differential gain error
Differential phase error
Aperture jitter
Sampling delay
Sym.
I
OH
IOL
IOZH
TDL
EL
ED
DG
DP
t
AJ
tDS
Conditions
OE=V ,
SS
VDD=min.
OE=VDD,
V =V -0.5V
OH DD
VOL=0.4V
VOH=VDD
V =0V
OL
F =5MSPS V =0.6V to 2.6V
C IN
FC=5MSPS VIN=0.6V to 2.6V
NTSC 40 IRE mod ramp,
F =14.3MSPS
C
Min. Typ. Max. Unit
-1.1 mA
3.7
16 uA
16
25 40 ns
0.5 1.3 LSB
±0.3 ±0.5 LSB
1.0 %
0.5 °C
30 ps
4 ns
Application Note
VDD,VSS
To reduce noise effects, separate the analog and digital systems close to the device. For both the digital and
analog VDD pins, use a ceramic capacitor of about 0.1uF set as close as possible to the pin to bypass to the
respective GND’s.
Analog input
Compared with the flash type A/D converter, the input capacitance of the analog input is rather small. However
it is necessary to conduct the drive with an amplifier featuring sufficient band and drive capability. When
driving with an amplifier of low output impedance, parasite oscillation may occur. That may be prevented by
inserting a resistance of about 100in series between the amplifier output and A/D input.
Clock input
The clock line wiring should be as short as possible also, to avoid any interference with other signals, separate
it from other circuits
Reference input
Voltage between VRT to VRB is compatible with the dynamic range of the analog input. Bypassing VRT and
V
RB
pins
to
GND,
by
means
of
a
capacitor
about
0.1µF,
stable
characteristics
are
obtained.
By
shorting
V
RT
and VRTS, VRB and VRBS, the self bias function that generates VRT=2.6V and VRB=0.6V, is activated.
Timing
Analog input is sampled with the falling edge of external clock and output as digital data with a delay of 2.5
clocks and with the following rising edge. The delay from the clock rising edge to the data output is about 25ns.
OE pin
By connecting OE to GND output mode is obtained. By connecting to VDD high impedance is obtained.
* This specification are subject to be changed without notice.
4.23.1997 4

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