Datasheet.kr   

EM636327JT-10 데이터시트 PDF




Etron Technology Inc.에서 제조한 전자 부품 EM636327JT-10은 전자 산업 및 응용 분야에서
광범위하게 사용되는 반도체 소자입니다.


PDF 형식의 EM636327JT-10 자료 제공

부품번호 EM636327JT-10 기능
기능 512K x 32 High Speed Synchronous Graphics DRAM(SGRAM)
제조업체 Etron Technology Inc.
로고 Etron Technology  Inc. 로고


EM636327JT-10 데이터시트 를 다운로드하여 반도체의 전기적 특성과 매개변수에 대해 알아보세요.



전체 70 페이지수

미리보기를 사용할 수 없습니다

EM636327JT-10 데이터시트, 핀배열, 회로
EtronTech
EM636327
512K x 32 High Speed Synchronous Graphics DRAM(SGRAM)
Preliminary (12/98)
Features
Fast access time from clock: 5/5/5.5/6.5/7.5 ns
Fast clock rate: 183/166/143/125/100 MHz
Fully synchronous operation
Internal pipelined architecture
Dual internal banks(256K x 32-bit x 2-bank)
Programmable Mode and Special Mode registers
- CAS# Latency: 1, 2, or 3
- Burst Length: 1, 2, 4, 8, or full page
- Burst Type: interleaved or linear burst
- Burst-Read-Single-Write
- Load Color or Mask register
Burst stop function
Individual byte controlled by DQM0-3
Block write and write-per-bit capability
Auto Refresh and Self Refresh
2048 refresh cycles/32ms
Single +3.3V±0.3V power supply
Interface: LVTTL
JEDEC 100-pin Plastic package
-QFP (body thickness=2.8mm)
-TQFP1.4 (body thickness=1.4mm)
-TQFP1.0 (body thickness=1.0mm)
Overview
The EM636327 SGRAM is a high-speed
CMOS synchronous graphics DRAM containing 16
Mbits. It is internally configured as a dual 256K x
32 DRAM with a synchronous interface (all signals
are registered on the positive edge of the clock
signal, CLK). Each of the 256K x 32 bit banks is
organized as 1024 rows by 256 columns by 32 bits.
Read and write accesses to the SGRAM are burst
oriented; accesses start at a selected location and
continue for a programmed number of locations in
a programmed sequence. Accesses begin with the
registration of a BankActivate command which is
then followed by a Read or Write command.
The EM636327 provides for programmable
Read or Write burst lengths of 1, 2, 4, 8, or full
Key Specifications
EM636327
- 55/6/7/8/10
tCK3 Clock Cycle time(min.)
5.5/6/7/8/10 ns
tRAS Row Active time(max.)
32/36/42/48/60 ns
tAC1 Access time from Read command 7/8/13/18/23 ns
tAC3 Access time from CLK(max.)
5/5/5.5/6.5/7.5 ns
tRC Row Cycle time(min.)
48/54/63/72/90 ns
Ordering Information
Part Number Frequency Package
EM636327Q-10
100MHz
QFP
EM636327R-10
100MHz QFP (Reverse)
EM636327TQ-10 100MHz
TQFP1.4
EM636327JT-10
100MHz
TQFP1.0
EM636327Q-8
125MHz
QFP
EM636327R-8
125MHz QFP (Reverse)
EM636327TQ-8
125MHz
TQFP1.4
EM636327JT-8
125MHz
TQFP1.0
EM636327Q-7
143MHz
QFP
EM636327TQ-7
143MHz
TQFP1.4
EM636327Q-6
166MHz
QFP
EM636327TQ-6
166MHz
TQFP1.4
EM636327Q-55
183MHz
QFP
EM636327TQ-55 183MHz
TQFP1.4
page, with a burst termination option. An auto
precharge function may be enabled to provide a
self-timed row precharge that is initiated at the end
of the burst sequence. The refresh functions,
either Auto or Self Refresh are easy to use. In
addition, EM636327 features the write-per-bit and
the masked block write functions.
By having a programmable mode register and
special mode register, the system can choose the
most suitable modes to maximize its performance.
These devices are well suited for applications
requiring high memory bandwidth, and when
combined with special graphics functions result in
a device particularly well suited to high
performance graphics applications.
Etron Technology, Inc.
1F, No. 1, Prosperity Rd. 1, Science-Based Industrial Park, Hsinchu, Taiwan, R.O.C
TEL: (886)-3-5782345 FAX: (886)-3-5779001
Etron Technology, Inc., reserves the right to make changes to its products and specifications without notice.




EM636327JT-10 pdf, 반도체, 판매, 대치품
EtronTech
EM636327
53 DSF Input Define Special Function: The DSF signal defines the operation commands
in conjunction with the RAS# and CAS# and WE# signals and is latched at
the positive edges of CLK. The DSF input is used to select the masked write
disable/enable command and block write command, and the Special Mode
Register Set cycle.
23, 56, 24, DQM0 - Input Data Input/Output Mask: DQM0-DQM3 are byte specific, nonpersistent I/O
57 DQM3
buffer controls. The I/O buffers are placed in a high-z state when DQM is
sampled HIGH. Input data is masked when DQM is sampled HIGH during a
write cycle. Output data is masked (two-clock latency) when DQM is sampled
HIGH during a read cycle. DQM3 masks DQ31-DQ24, DQM2 masks DQ23-
DQ16, DQM1 masks DQ15-DQ8, and DQM0 masks DQ7-DQ0.
97, 98, 100,
1, 3, 4, 6 , 7,
60, 61, 63,
64, 68, 69,
71, 72, 9,
10, 12, 13,
17, 18, 20,
21, 74, 75,
77, 78, 80,
81, 83, 84
DQ0-
DQ31
Input/ Data I/O: The DQ0-31 input and output data are synchronized with the
Output positive edges of CLK. The I/Os are byte-maskable during Reads and Writes.
The DQs also serve as column/byte mask inputs during Block Writes.
36-45, 52, NC
58, 86-95
- No Connect: These pins should be left unconnected.
2, 8, 14, 22, VDDQ Supply DQ Power: Provide isolated power to DQs for improved noise immunity.
59, 67, 73,
79
5, 11, 19,
62, 70, 76,
82, 99
VSSQ Supply DQ Ground: Provide isolated ground to DQs for improved noise immunity.
15, 35, 65, VDD Supply Power Supply: +3.3V±0.3V
96
16, 46, 66, VSS Supply Ground
85
Preliminary
4 December 1998

4페이지










EM636327JT-10 전자부품, 판매, 대치품
EtronTech
EM636327
into high-impedance at the end of the burst unless other command is initiated. The burst length,
burst sequence, and CAS# latency are determined by the mode register, which is already
programmed. A full-page burst will continue until terminated (at the end of the page it will wrap to
column 0 and continue).
T0 T1
T2 T3
T4 T5
T6 T7
T8
CLK
C OM M A ND
READ A
CAS# latency=1
tCK1, DQ's
CAS# latency=2
tCK2, DQ's
CAS# latency=3
tCK3, DQ's
NOP
NOP
NOP
NOP
NOP
NOP
NOP
DOUT A0 DOUT A1
DOUT A2 DOUT A3
DOUT A0 DOUT A1
DOUT A2 DOUT A3
DOUT A0 DOUT A1
DOUT A2 DOUT A3
NOP
Burst Read Operation(Burst Length = 4, CAS# Latency = 1, 2, 3)
The read data appears on the DQs subject to the values on the DQM inputs two clocks earlier
(i.e. DQM latency is two clocks for output buffers). A read burst without the auto precharge function
may be interrupted by a subsequent Read or Write/Block Write command to the same bank or the
other active bank before the end of the burst length. It may be interrupted by a BankPrecharge/
PrechargeAll command to the same bank too. The interrupt coming from the Read command can
occur on any clock cycle following a previous Read command (refer to the following figure).
T0 T1
T2 T3
T4 T5
T6 T7
T8
CLK
C OM M A ND
READ A
READ B
NOP
NOP
NOP
NOP
NOP
NOP
NOP
CAS# latency=1
tCK1, DQ's
CAS# latency=2
tCK2, DQ's
CAS# latency=3
tCK3, DQ's
DOUT A0 DOUT B0
DOUT B1
DOUT B2
DOUT B3
DOUT A0 DOUT B0
DOUT B1
DOUT B2
DOUT B3
DOUT A0 DOUT B0
DOUT B1
DOUT B2
DOUT B3
Read Interrupted by a Read (Burst Length = 4, CAS# Latency = 1, 2, 3)
The DQM inputs are used to avoid I/O contention on the DQ pins when the interrupt comes
from a Write/Block Write command. The DQMs must be asserted (HIGH) at least two clocks prior to
the Write/Block Write command to suppress data-out on the DQ pins. To guarantee the DQ pins
against I/O contention, a single cycle with high-impedance on the DQ pins must occur between the
last read data and the Write/Block Write command (refer to the following three figures). If the data
output of the burst read occurs at the second clock of the burst write, the DQMs must be asserted
(HIGH) at least one clock prior to the Write/Block Write command to avoid internal bus contention.
Preliminary
7 December 1998

7페이지


구       성 총 70 페이지수
다운로드[ EM636327JT-10.PDF 데이터시트 ]

당사 플랫폼은 키워드, 제품 이름 또는 부품 번호를 사용하여 검색할 수 있는

포괄적인 데이터시트를 제공합니다.


구매 문의
일반 IC 문의 : 샘플 및 소량 구매
-----------------------------------------------------------------------

IGBT, TR 모듈, SCR 및 다이오드 모듈을 포함한
광범위한 전력 반도체를 판매합니다.

전력 반도체 전문업체

상호 : 아이지 인터내셔날

사이트 방문 :     [ 홈페이지 ]     [ 블로그 1 ]     [ 블로그 2 ]



관련 데이터시트

부품번호상세설명 및 기능제조사
EM636327JT-10

512K x 32 High Speed Synchronous Graphics DRAM(SGRAM)

Etron Technology  Inc.
Etron Technology Inc.

DataSheet.kr       |      2020   |     연락처      |     링크모음      |      검색     |      사이트맵