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PDF EM636327R-10 Data sheet ( Hoja de datos )
| Número de pieza | EM636327R-10 | |
| Descripción | 512K x 32 High Speed Synchronous Graphics DRAM(SGRAM) | |
| Fabricantes | Etron Technology Inc. | |
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EtronTech
EM636327
512K x 32 High Speed Synchronous Graphics DRAM(SGRAM)
Preliminary (12/98)
Features
• Fast access time from clock: 5/5/5.5/6.5/7.5 ns
• Fast clock rate: 183/166/143/125/100 MHz
• Fully synchronous operation
• Internal pipelined architecture
• Dual internal banks(256K x 32-bit x 2-bank)
• Programmable Mode and Special Mode registers
- CAS# Latency: 1, 2, or 3
- Burst Length: 1, 2, 4, 8, or full page
- Burst Type: interleaved or linear burst
- Burst-Read-Single-Write
- Load Color or Mask register
• Burst stop function
• Individual byte controlled by DQM0-3
• Block write and write-per-bit capability
• Auto Refresh and Self Refresh
• 2048 refresh cycles/32ms
• Single +3.3V±0.3V power supply
• Interface: LVTTL
• JEDEC 100-pin Plastic package
-QFP (body thickness=2.8mm)
-TQFP1.4 (body thickness=1.4mm)
-TQFP1.0 (body thickness=1.0mm)
Overview
The EM636327 SGRAM is a high-speed
CMOS synchronous graphics DRAM containing 16
Mbits. It is internally configured as a dual 256K x
32 DRAM with a synchronous interface (all signals
are registered on the positive edge of the clock
signal, CLK). Each of the 256K x 32 bit banks is
organized as 1024 rows by 256 columns by 32 bits.
Read and write accesses to the SGRAM are burst
oriented; accesses start at a selected location and
continue for a programmed number of locations in
a programmed sequence. Accesses begin with the
registration of a BankActivate command which is
then followed by a Read or Write command.
The EM636327 provides for programmable
Read or Write burst lengths of 1, 2, 4, 8, or full
Key Specifications
EM636327
- 55/6/7/8/10
tCK3 Clock Cycle time(min.)
5.5/6/7/8/10 ns
tRAS Row Active time(max.)
32/36/42/48/60 ns
tAC1 Access time from Read command 7/8/13/18/23 ns
tAC3 Access time from CLK(max.)
5/5/5.5/6.5/7.5 ns
tRC Row Cycle time(min.)
48/54/63/72/90 ns
Ordering Information
Part Number Frequency Package
EM636327Q-10
100MHz
QFP
EM636327R-10
100MHz QFP (Reverse)
EM636327TQ-10 100MHz
TQFP1.4
EM636327JT-10
100MHz
TQFP1.0
EM636327Q-8
125MHz
QFP
EM636327R-8
125MHz QFP (Reverse)
EM636327TQ-8
125MHz
TQFP1.4
EM636327JT-8
125MHz
TQFP1.0
EM636327Q-7
143MHz
QFP
EM636327TQ-7
143MHz
TQFP1.4
EM636327Q-6
166MHz
QFP
EM636327TQ-6
166MHz
TQFP1.4
EM636327Q-55
183MHz
QFP
EM636327TQ-55 183MHz
TQFP1.4
page, with a burst termination option. An auto
precharge function may be enabled to provide a
self-timed row precharge that is initiated at the end
of the burst sequence. The refresh functions,
either Auto or Self Refresh are easy to use. In
addition, EM636327 features the write-per-bit and
the masked block write functions.
By having a programmable mode register and
special mode register, the system can choose the
most suitable modes to maximize its performance.
These devices are well suited for applications
requiring high memory bandwidth, and when
combined with special graphics functions result in
a device particularly well suited to high
performance graphics applications.
Etron Technology, Inc.
1F, No. 1, Prosperity Rd. 1, Science-Based Industrial Park, Hsinchu, Taiwan, R.O.C
TEL: (886)-3-5782345 FAX: (886)-3-5779001
Etron Technology, Inc., reserves the right to make changes to its products and specifications without notice.
1 page  
EtronTech
EM636327
Operation Mode
Fully synchronous operations are performed to latch the commands at the positive edges of CLK.
Table 2 shows the truth table for the operation commands.
Table 2. Truth Table (Note (1), (2) )
Command
State CKEn-1 CKEn DQM(7) BS A9 A0-8 CS# RAS# CAS# WE# DSF
BankActivate & Masked Write Disable
Idle(3)
H
X
X VV V L L
H HL
BankActivate & Masked Write Enable
Idle(3)
H
X
X VV V L L
H HH
BankPrecharge
Any H X X V L X L L H L L
PrechargeAll
Any H X X X H X L L H L L
W rite
Active(3) H X X V L V L H L L L
Block Write Command
Active(3) H X X V L V L H L L H
Write and AutoPrecharge
Active(3) H X X V H V L H L L L
Block Write and AutoPrecharge
Active(3) H X X V H V L H L L H
Read
Active(3) H X X V L V L H L H L
Read and Autoprecharge
Active(3) H X X V H V L H L H L
Mode Register Set
Idle H X X V L V L L L L L
Special Mode Register Set
Idle(5) H X X X X V L L L L H
No-Operation
Any H X X X X X L H H H X
Burst Stop
Active(4) H X X X X X L H H L L
Device Deselect
Any H X X X X X H X X X X
AutoRefresh
Idle H H X X X X L L L H L
SelfRefresh Entry
Idle H L X X X X L L L H L
SelfRefresh Exit
Idle L H X X X X H X X X X
(SelfRefresh)
L H H HX
Clock Suspend Mode Entry
Active H L X X X X X X X X X
Power Down Mode Entry
Any(6) H L X X X X H X X X X
L H H HL
Clock Suspend Mode Exit
Active L H X X X X X X X X X
Power Down Mode Exit
Any L H X X X X H X X X X
(PowerDown)
L H H HL
Data Write/Output Enable
Active H X L X X X X X X X X
Data Mask/Output Disable
Active H X H X X X X X X X
Note:
1. V=Valid X=Don't Care L=Low level H=High level
2. CKEn signal is input level when commands are provided.
CKEn-1 signal is input level one clock cycle before the commands are provided.
3. These are states of bank designated by BS signal.
4. Device state is 1, 2, 4, 8, and full page burst operation.
5. The Special Mode Register Set is also available in Row Active State.
6. Power Down Mode can not enter in the burst operation.
When this command is asserted in the burst cycle, device state is clock suspend mode.
7. DQM0-3
X
Preliminary
5 December 1998
5 Page 
EtronTech
EM636327
first read data appears on the outputs (refer to the following figure). Once the Read command is
registered, the data inputs will be ignored and writes will not be executed.
T0 T1
T2 T3
T4 T5
T6 T7
T8
CLK
COM MAND
NOP
WRITE A READ B
NOP
NOP
NOP
NOP
NOP
NOP
CAS# latency=1
tCK1, DQ's
CAS# latency=2
tCK2, DQ's
CAS# latency=3
tCK3, DQ's
DIN A0
DOUT B0 DOUT B1
DOUT B2 DOUT B3
DIN A0
don't care
DOUT B0
DOUT B1
DOUT B2 DOUT B3
DIN A0
don't care don't care
Input data for the write is masked.
DOUT B0
DOUT B1 DOUT B2 DOUT B3
Input data must be removed from the DQ's at least one clock
cycle before the Read data appears on the outputs to avoid
data contention.
Write Interrupted by a Read (Burst Length = 4, CAS# Latency = 1, 2, 3)
The BankPrecharge/PrechargeAll command that interrupts a write burst without the auto
precharge function should be issued m cycles after the clock edge in which the last data-in element
is registered, where m equals tWR/tCK rounded up to the next whole number. In addition, the DQM
signals must be used to mask input data, starting with the clock edge following the last data-in
element and ending with the clock edge on which the BankPrecharge/PrechargeAll command is
entered (refer to the following figure).
T0 T1
T2 T3 T4 T5
T6
CLK
DQM
C OM M A ND
WRITE
NOP
Precharge
tRP
NOP NOP
Activate
NOP
ADDRESS
DQ
BANK
COL n
DIN
n
BANK (S)
tWR
DIN
n+1
ROW
: don't care
Note: The DQMs can remain low in this example if the length of the write burst is 1 or 2.
Write to Precharge
When the Burst-Read-Single-Write mode is selected, the write burst length is 1 regardless of
the read burst length (refer to Figures 21 and 22 in Timing Waveforms).
8 Block Write command
(RAS# = "H", CAS# = "L", WE# = "L", DSF = "H", BS = Bank, A9 = "L", A3-A7 = Column Address,
DQ0-DQ31 = Column Mask)
The block writes are non-burst accesses that write to eight column locations simultaneously. A
single data value, which was previously loaded in the Color register, is written to the block of eight
consecutive column locations addressed by inputs A3~A7. The information on the DQs which are
Preliminary
11 December 1998
11 Page | ||
| Páginas | Total 70 Páginas | |
| PDF Descargar | [ Datasheet EM636327R-10.PDF ] | |
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