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EM6A9320 데이터시트 PDF




Etron Technology Inc.에서 제조한 전자 부품 EM6A9320은 전자 산업 및 응용 분야에서
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부품번호 EM6A9320 기능
기능 4M x 32 DDR SDRAM
제조업체 Etron Technology Inc.
로고 Etron Technology  Inc. 로고


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EM6A9320 데이터시트, 핀배열, 회로
Et r onT ec h
Etron Confidential
Features
EM6A9320
4M x 32 DDR SDRAM
Preliminary (Rev 0.3 7/2002)
Overview
Fast clock rate: 350/333/300/285/250/200 MHz
Differential Clock CK & CK# input
4 Bi-directional DQS. Data transactions on both
edges of DQS (1DQS / Byte)
DLL aligns DQ and DQS transitions
Edge aligned data & DQS output
Center aligned data & DQS input
4 internal banks, 1M x 32-bit for each bank
Programmable mode and extended mode registers
- CAS# Latency: 3, 4, 5
- Burst length: 2, 4, 8
- Burst Type: Sequential & Interleave
Full page burst length for sequential type only
Start address of full page burst should be even
All inputs except DQ’s & DM are at the positive
edge of the system clock
No Write-Interrupted by Read function
4 individual DM control for write masking only
Auto Refresh and Self Refresh
4096 refresh cycles / 32ms
Power supplies up to 350/333/300/285MHz:
VDD = 2.8V ± 5%
VDDQ = 2.8V ± 5%
Power supplies up to 250/200MHz:
VDD = 2.5V ± 5%
The EM6A9320 DDR SDRAM is a high-speed CMOS
double data rate synchronous DRAM containing 128
Mbits. It is internally configured as a quad 1M x 32
DRAM with a synchronous interface (all signals are
registered on the positive edge of the clock signal, CK).
Data outputs occur at both rising edges of CK and CK#.
Read and write accesses to the SDRAM are burst
oriented; accesses start at a selected location and
continue for a programmed number of locations in a
programmed sequence.
Accesses begin with the registration of a BankActivate
command, which is then followed by a Read or Write
command.
The EM6A9320 provides programmable Read or Write
burst lengths of 2, 4, 8. An auto precharge function may
be enabled to provide a self-timed row precharge that is
initiated at the end of the burst sequence.
The refresh functions, either Auto or Self Refresh are
easy to use.
In addition, EM6A9320 features programmable DLL
option. By having a programmable mode register and
extended mode register, the system can choose the
most suitable modes to maximize its performance.
These devices are well suited for applications requiring
high memory bandwidth, result in a device particularly
well suited to high performance main memory and
graphics applications.
VDDQ = 2.5V ± 5%
Interface : SSTL_2 I/O compatible
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Ordering Information
Part Number
EM6A9320BI-2.8
EM6A9320BI-3.0
EM6A9320BI-3.3
EM6A9320BI-3.5
EM6A9320BI-4
EM6A9320BI-5
Frequency
350MHz
333MHz
300MHz
285MHz
250MHz
200MHz
Power Supply
VDD 2.8V
VDDQ 2.8V
VDD 2.5V
VDDQ 2.5V
Package
FBGA
FBGA
FBGA
FBGA
FBGA
FBGA
Etron Technology, Inc.
No. 6, Technology Rd. V, Science-Based Industrial Park, Hsinchu, Taiwan 30077, R.O.C.
TEL: (886)-3-5782345 FAX: (886)-3-5778671
Etron Technology, Inc., reserves the right to make changes to its products and specifications without notice.




EM6A9320 pdf, 반도체, 판매, 대치품
Et r onT ec h
4Mx32 DDR SDRAM
EM6A9320
Pin Descriptions
Table 1. Pin Details of EM6A9320
Symbol
CK, CK#
CKE
BA0, BA1
A0-A11
CS#
RAS#
CAS#
WE#
DQS0-DQS3
DM0 - DM3
DQ0 - DQ31
VDD
Type
Input
Input
Input
Input
Input
Input
Input
Input
Input /
Output
Input
Input /
Output
Supply
Description
Differential Clock: CK, CK# are driven by the system clock. All SDRAM input
commands are sampled on the positive edge of CK. Both CK and CK# increment the
internal burst counter and controls the output registers.
Clock Enable: CKE activates (HIGH) and deactivates (LOW) the CK signal. If CKE
goes low synchronously with clock, the internal clock is suspended from the next clock
cycle and the state of output and burst address is frozen as long as the CKE remains
low. When all banks are in the idle state, deactivating the clock controls the entry to
the Power Down and Self Refresh modes.
Bank Select: BA0 and BA1 defines to which bank the BankActivate, Read, Write, or
BankPrecharge command is being applied. They also define which Mode Register or
Extended Mode Register is loaded during a Mode Register Set command.
Address Inputs: A0-A11 are sampled during the Bank Activate command (row
address A0-A11) and Read/Write command (column address A0-A7 with A8 defining
Auto Precharge) to select one location out of the 256K available in the respective
bank. During a Precharge command, A8 is sampled to determine if all banks are to be
precharged (A8 = HIGH). The address inputs also provide the op-code during a Mode
Register Set or Extended Mode Register Set command.
Chip Select: CS# enables (sampled LOW) and disables (sampled HIGH) the
command decoder. All commands are masked when CS# is sampled HIGH. CS#
provides for external bank selection on systems with multiple banks. It is considered
part of the command code.
Row Address Strobe: The RAS# signal defines the operation commands in
conjunction with the CAS# and WE# signals and is latched at the positive edges of
CK. When RAS# and CS# are asserted "LOW" and CAS# is asserted "HIGH" either
the BankActivate command or the Precharge command is selected by the WE# signal.
When the WE# is asserted "HIGH," the BankActivate command is selected and the
bank designated by BS is turned on to the active state. When the WE# is asserted
"LOW," the Precharge command is selected and the bank designated by BS is
switched to the idle state after the precharge operation.
Column Address Strobe: The CAS# signal defines the operation commands in
conjunction with the RAS# and WE# signals and is latched at the positive edges of
CK. When RAS# is held "HIGH" and CS# is asserted "LOW" the column access is
started by asserting CAS# "LOW" Then, the Read or Write command is selected by
asserting WE# "HIGH " or LOW".
Write Enable: The WE# signal defines the operation commands in conjunction with
the RAS# and CAS# signals and is latched at the positive edges of CK. The WE#
input is used to select the BankActivate or Precharge command and Read or Write
command.
Bidirectional Data Strobe: The DQSx signals are mapped to the following data
bytes: DQS0 to DQ0-DQ7, DQS1 to DQ8-DQ15, DQS2 to DQ16-DQ23, DQS3 to
DQ24-DQ31.
Data Input Mask: DM0-DM3 are byte specific. Input data is masked when DM is
sampled HIGH during a write cycle. DM3 masks DQ31-DQ24, DM2 masks DQ23-
DQ16, DM1 masks DQ15-DQ8, and DM0 masks DQ7-DQ0.
Data I/O: The DQ0-DQ31 input and output data are synchronized with the positive
edges of CK and CK#. The I/Os are byte-maskable during Writes.
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Etron Confidential
4
Rev 0.3
July. 2002

4페이지










EM6A9320 전자부품, 판매, 대치품
Et r onT ec h
4Mx32 DDR SDRAM
EM6A9320
Extended Mode Register Set (EMRS)
The Extended Mode Register Set stores the data for enabling or disabling DLL and selecting output driver
strength. The default value of the extended mode register is not defined, therefore must be written after power
up for proper operation. The extended mode register is written by asserting low on CS#, RAS#, CAS#, and WE#.
The state of A0, A2 ~ A5, A7 ~ A11and BA1 is written in the mode register in the same cycle as CS#, RAS#,
CAS#, and WE# going low. The DDR SDRAM should be in all bank precharge with CKE already high prior to
writing into the extended mode register. A1 and A6 are used for setting driver strength to normal, weak or
matched impedance. Two clock cycles are required to complete the write operation in the extended mode
register. The mode register contents can be changed using the same command and clock cycle requirements
during operation as long as all banks are in the idle state. A0 is used for DLL enable or disable. "High" on BA0 is
used for EMRS. Refer to the table for specific codes.
Extended Mode Resistor Bitmap
BA1 BA0 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
01
RFU must be set to 0
DS1 RFU must be set to 0DS0 DLL
BA0 Mode
0 MRS
1 EMRS
A6 A1 Drive Strength Strength
Comment
00
Full
100%
0 1 SSTL-2 weak
60%
10
RFU
RFU Do not use
1 1 Matched impedance 30% Output driver matches impedance
A0 DLL
0 Enable
1 Disable
Power up Sequence
Power up must be performed in the following sequence.
1) Apply power to VDD before or at the same time as VDDQ, VTT and VREF when all input signals are held
"NOP" state and maintain CKE LOW.
2) Start clock and maintain stable condition for minimum 200us.
3) Issue a NOPcommand and keep CKE HIGH
4) Issue a Precharge Allcommand.
5) Issue EMRS enable DLL.
6) Issue MRS reset DLL. (An additional 200 clock cycles are required to lock the DLL).
7) Precharge all banks of the device.
8) Issue two or more Auto Refresh commands.
9) Issue MRS with A8 to low to initialize the mode register.
Etron Confidential
7
Rev 0.3
July. 2002

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부품번호상세설명 및 기능제조사
EM6A9320

4M x 32 DDR SDRAM

Etron Technology  Inc.
Etron Technology Inc.
EM6A9320BIB

4M x 32 bit DDR Synchronous DRAM

Etron Technology
Etron Technology

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