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PDF DSP101 Data sheet ( Hoja de datos )
| Número de pieza | DSP101 | |
| Descripción | DSP-Compatible Sampling Single/Dual ANALOG-TO-DIGITAL CONVERTERS | |
| Fabricantes | Burr-Brown Corporation | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de DSP101 (archivo pdf) en la parte inferior de esta página. Total 22 Páginas | ||
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® DSP101
DSP102
DSP-Compatible Sampling Single/Dual
ANALOG-TO-DIGITAL CONVERTERS
FEATURES
q ZERO-CHIP INTERFACE TO STANDARD
DSP ICs: AD, AT&T, MOTOROLA, TI
q SINGLE CHANNEL: DSP101
q DUAL CHANNEL: DSP102
Two Serial Outputs or Cascade to Single
32-Bit Word
q SAMPLING RATE TO 200kHz
q DYNAMIC SPECIFICATIONS:
Signal/(Noise + Distortion) = 88dB;
Spurious-Free Dynamic Range = 94dB;
THD = –91dB
q SERIAL OUTPUT DATA COMPATIBLE
WITH 16-, 24-, AND 32-BIT DSP IC
FORMATS
Analog
Input
Channel A
Analog
Input
Channel B
18-Bit Sampling ADC
Reference
18-Bit Sampling ADC
Channel B on DSP102 Only
DESCRIPTION
The DSP101 and DSP102 are high performance sam-
pling analog-to-digital converters designed for sim-
plicity of use with modern digital signal processing
ICs. Both are complete with all interface logic for use
directly with DSP ICs, and provide full sampling and
conversion at rates up to 200kHz.
The DSP101 offers a single conversion channel, with
18 bits of serial data output, allowing the user to drive
16-bit, 24-bit, or 32-bit DSP ports. The DSP102 offers
two complete conversion channels, with either two
full 18-bit output ports, or a mode to cascade two
16-bit conversions into a 32-bit port as one word.
Both the DSP101 and DSP102 are packaged in stan-
dard, low-cost 28-pin plastic DIP packages. Each is
offered in two performance grades to match applica-
tion requirements.
Convert
Command
Control
Logic
Select Sync Format
Channel A User Tag In
Channel A Data/
Cascaded Data
Sync
Bit Clock
Channel B Data
Channel B User Tag In
Cascade
International Airport Industrial Park • Mailing Address: PO Box 11400 • Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd. • Tucson, AZ 85706
Tel: (520) 746-1111 • Twx: 910-952-1111 • Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132
©1990 Burr-Brown Corporation
PDS-1068C
Printed in U.S.A. October. 1993
1 page  
TYPICAL DSP102 FFT SETUP
Brüel & Kjaer
Model 1049 1kHz
Digital Signal ±2.75V
Generator
6 Pole,
150kHz
Low-Pass
Filter
1/2
OPA2604
1/2
OPA2604
150Ω
150Ω
DSP102
27 REF
0.1µF
220pF
2
VINA
CASC
SSF
OSC1
CLKOUT
1
+ VPOTA CLKIN
10µF
22
12
13
11
10
+5V
16MHz TTL Oscillator
÷80 ÷2
220pF
25
VINB
26
CONV
XCLK
VPOTB SYNC
+
10µF
SOUTA
21 200kHz
16 8MHz
15
20
Burr-Brown
ZPB34
DSP
Processor
FFT
Software
ABSOLUTE MAXIMUM RATINGS
VA+ to Analog Common .................................................................... +7V
VA– to Analog Common .................................................................... –7V
VD to Digital Common ........................................................................ +7V
Analog Common to Digital Common ................................................... ±1V
Control Inputs to Digital Common ............................... –0.5 to VD + 0.5V
Analog Input Voltage .......................................................................... ±5V
Maximum Junction Temperature .................................................... 150oC
Internal Power Dissipation ............................................................. 825mW
Lead Temperature (soldering, 10s) ............................................... +300oC
Thermal Resistance, θJA, Plastic DIP ............................................ 50oC/W
DSP101 PIN CONFIGURATION
Top View
VPOT 1
VIN 2
MSB 3
VOS 4
VA – 5
VA+ 6
DGND 7
DGND 8
VD 9
CLKIN 10
CLKOUT 11
SSF 12
OSC1 13
OSC2 14
DSP101
DIP
28 AGND
27 REF
26 CAP
25
24
23
22 DGND
21 CONV
20 SOUT
19
18 TAG
17
16 XCLK
15 SYNC
DSP101 PIN ASSIGNMENTS
PIN #
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
NAME
VPOT
VIN
MSB
VOS
VA–
VA+
DGND
DGND
VD
CLKIN
CLKOUT
SSF
OSC1
OSC2
SYNC
XCLK
TAG
SOUT
CONV
DGND
CAP
REF
AGND
DESCRIPTION
Trim Reference Out. 10µF Tantalum to AGND.
Voltage on this pin is approximately 2.75V.
Analog In.
MSB Adjust In.
VOS Adjust In.
–5V Analog Power.
+5V Analog Power.
Digital Ground.
Digital Ground.
+5V Digital Power.
Conversion Clock In.
Conversion Clock Out. Can drive multiple
DSP101/DSP102s to synchronize conversion.
Select Synch Format In. If HIGH, SYNC will be
active High. If LOW, SYNC will be active Low.
See timing diagram (Figure 1).
Oscillator Point 1 Input/External Clock In. If using
external clock, drive with 74HC logic levels.
Connect to DGND if not used.
Oscillator Point 2 Output. Provides drive for
crystal oscillator. Make no electrical connection if
using external clock.
Data Synchronization Out. Active High when SSF
is HIGH; active Low when SSF is LOW.
Data Transfer Clock In.
No Internal Connection.
User Tag In. Data clocked into this pin is
appended to the conversion results on SOUT.
See timing diagram (Figure 1).
No Internal Connection.
Serial Data Out. MSB first, Binary Two’s
Complement format.
Convert Command In. Falling edge puts converter
into hold state, initiates conversion, and transmits
previous conversion results to DSP IC with
appropriate SYNC pulse.
Digital Ground.
No Internal Connection.
No Internal Connection.
No Internal Connection.
Bypass Capacitor. 10µF Tantalum to AGND.
Voltage on this pin is approximately 2.7V.
Reference Bypass. 0.1µF Ceramic to AGND.
Voltage on this pin is approximately 3.8V.
Analog Ground.
®
5 DSP101/102
5 Page 
During the internal successive approximation conversion
process, the conversion results are shifted into the input shift
registers of the output stage on the DSP102. A new convert
command latches that data into the 18-bit parallel latches
shown. The internal signal that also generates the Sync
pulse, labeled “Shift/Load” in Figure 4, synchronously loads
the conversion data into the output shift register on the rising
edge of XCLK. The conversion results are then clocked out
of the shift register on subsequent rising edges of XCLK.
DATA TRANSFER CLOCK
XCLK is the data transfer clock, or bit clock, for the system,
and is an input for the DSP101 or DSP102. This input is
TTL- and 74HC-level compatible. The serial data and SYNC
outputs are synchronized internally to this clock, with data
valid on the rising edge of XCLK, per the timing shown in
Figure 1. Data input on pin 18 (TAG) on the DSP101, or on
pins 18 and 19 on the DSP102 (TAGA and TAGB), will be
clocked into the output shift register on the rising edge of
XCLK, as discussed in the Tag Feature section.
CONVERSION CLOCK
The analog-to-digital converter sections in the DSP101 and
DSP102 were designed to provide accurate conversions
under worst case conditions of supplies, temperatures, etc.
In order to achieve a full 200kHz sampling capability, they
were designed to use a 33% duty cycle conversion clock
(CLKIN on pin 10) as shown in Figure 1. The clock is LOW
long enough for internal analog circuitry to settle suffi-
ciently between bit decisions to insure rated accuracy. Bit
decisions in the A/D are then made on the rising edge of
CLKIN.
DSP101 or DSP102
SAR Clock
Control
CLKIN
To other
DSP102's CLKIN for
synchronous operation
10
CLKOUT 11
÷3
OSC1
13
1MΩ
14
OSC2
12.288MHz
10pF
10pF
Crystal is CTS Knight MP122 12.288MHz,
20pF load, series resonant mode.
FIGURE 5. DSP101 or DSP102 Conversion Clock Circuit.
DSP101 or DSP102
+
10µF
(1)
–5V Analog
+5V Analog
+
10Ω(2)
+
10µF
+5V Digital
10µF 0.01µF
1 VPOTA
2
3
4
5 VA –
6 VA +
7 DGND
8 DGND
9 VD
10
11
12
13
14
AGND
REF
VPOTB
28
27
0.1µF
26 +
10µF
25
(1)
24
23
22
21
20
19
18
17
16 = Analog Ground
15 = Digital Ground
NOTES: (1) Pin 1 and pin 26 must be bypassed with 10µF tantalum capacitors, on both the DSP101 and DSP102.
(2) Protection from power supply momentary overrange.
FIGURE 6. DSP101 or DSP102 Power Supply Connections.
11 DSP101/102
®
11 Page | ||
| Páginas | Total 22 Páginas | |
| PDF Descargar | [ Datasheet DSP101.PDF ] | |
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