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PDF DSP56374UM Data sheet ( Hoja de datos )
| Número de pieza | DSP56374UM | |
| Descripción | high density CMOS device with 3.3 V inputs and outputs | |
| Fabricantes | Motorola Inc | |
| Logotipo |  |
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Freescale Semiconductor
Technical Data
DSP56374
Rev. 1, 11/2004
Overview
The DSP56374 is a high density CMOS device with 3.3 V inputs and outputs.
NOTE
This document contains information on a new product.
Specifications and information herein are subject to
change without notice.
Finalized specifications may be published after further characterization and device
qualifications are completed.
The DSP56374 supports digital audio applications requiring sound field processing,
acoustic equalization, and other digital audio algorithms. The DSP56374 uses the high
performance, single-clock-per-cycle DSP56300 core family of programmable CMOS digital
signal processors (DSPs) combined with the audio signal processing capability of the
Freescale Semiconductor, Inc. (formerly Motorola) Symphony™ DSP family, as shown in
Figure 1. Significant architectural enhancements include a barrel shifter, 24-bit addressing,
and direct memory access (DMA). The DSP56374 offers 150 million instructions per second
(MIPS) using an internal 150 MHz clock.
Data Sheet Conventions
This data sheet uses the following conventions:
OVERBAR Used to indicate a signal that is active when pulled low (For
example, the RESET pin is active when low.)
“asserted” Means that a high true (active high) signal is high or that a low true
(active low) signal is low
“deasserted” Means that a high true (active high) signal is low or that a low true
(active low) signal is high
Table of Contents
Section
Page
1 Features........................................ 2
2 Documentation.............................. 4
3 Signal Groupings .......................... 4
4 Maximum Ratings ....................... 24
5 Power Requirements................... 25
6 Thermal Characteristics.............. 26
7 DC Electrical Characteristics ...... 26
8 AC Electrical Characteristics....... 27
9 Internal Clocks ............................ 27
10 External Clock Operation .......... 29
11 Reset, Stop, Mode Select, and
Interrupt Timing ........................... 30
12 Serial Host Interface SPI Protocol
Timing.......................................... 34
13 Serial Host Interface (SHI) I2C
Protocol Timing ........................... 40
14 Programming the Serial Clock .. 42
15 Enhanced Serial Audio Interface
Timing.......................................... 43
16 Timer Timing ............................. 48
17 GPIO Timing ............................. 48
18 JTAG Timing ............................. 50
19 Watchdog Timer Timing ............ 52
Appendix A Package Information. 53
Appendix B IBIS Model ................. 63
Examples:
Signal/
Symbol
Logic State Signal State
Voltage*
PIN
True
Asserted
VIL / VOL
PIN
False
Deasserted
VIH / VOH
PIN
True
Asserted
VIH / VOH
PIN
False
Deasserted
VIL / VOL
Note: *Values for VIL, VOL, VIH, and VOH are defined by individual product specifications.
© Freescale Semiconductor, Inc., 2004. All rights reserved.
PRELIMINARY
1 page  
Signal Groupings
3.1 Power
Table 4. Power Inputs
Power Name
Description
PLLA_VDD (1)
PLL Power— The voltage (3.3 V) should be well-regulated and the input should be provided with
an extremely low impedance path to the 3.3 VDD power rail. The user must provide adequate
external decoupling capacitors between PLLA_VDD and PLLA_GND. PLLA_VDD requires a
filter as shown in Figure 21 and Figure 22 below. See the DSP56374 technical data sheet for
additional details.
PLLP_VDD(1)
PLL Power— The voltage (3.3 V) should be well-regulated and the input should be provided with
an extremely low impedance path to the 3.3 VDD power rail. The user must provide adequate
external decoupling capacitors between PLLP_VDD and PLLP_GND.
PLLD_VDD (1)
PLL Power— The voltage (1.25 V) should be well-regulated and the input should be provided
with an extremely low impedance path to the 1.25 VDD power rail. The user must provide
adequate external decoupling capacitors between PLLD_VDD and PLLD_GND.
CORE_VDD (4) Core Power—The voltage (1.25 V) should be well-regulated and the input should be provided
with an extremely low impedance path to the 1.25 VDD power rail. The user must provide
adequate external decoupling capacitors.
IO_VDD
(80-pin 4)
(52-pin 3)
SHI, ESAI, ESAI_1, WDT and Timer I/O Power —The voltage (3.3 V) should be well-regulated,
and the input should be provided with an extremely low impedance path to the 3.3 VDD power
rail. This is an isolated power for the SHI, ESAI, ESAI_1, WDT and Timer I/O. The user must
provide adequate external decoupling capacitors.
3.2 Ground
Table 5. Grounds
Ground Name
Description
PLLA_GND(1)
PLL Ground—The PLL ground should be provided with an extremely low-impedance path to
ground. This connection must be tied externally to all other chip ground connections. The user
must provide adequate external decoupling capacitors between PLLA_VDD and PLLA_GND.
PLLP_GND(1)
PLL Ground—The PLL ground should be provided with an extremely low-impedance path to
ground. This connection must be tied externally to all other chip ground connections. The user
must provide adequate external decoupling capacitors between PLLP_VDD and PLLP_GND.
PLLD_GND(1)
PLL Ground—The PLL ground should be provided with an extremely low-impedance path to
ground. This connection must be tied externally to all other chip ground connections. The user
must provide adequate external decoupling capacitors between PLLD_VDD and PLLD_GND.
CORE_GND(4) Core Ground—The Core ground should be provided with an extremely low-impedance path to
ground. This connection must be tied externally to all other chip ground connections. The user
must provide adequate external decoupling capacitors.
IO_GND(2)
SHI, ESAI, ESAI_1, WDT and Timer I/O Ground—IO_GND is the ground for the SHI, ESAI,
ESAI_1, WDT and Timer I/O. This connection must be tied externally to all other chip ground
connections. The user must provide adequate external decoupling capacitors.
Freescale Semiconductor
PRELIMINARY
5
5 Page 
Signal Groupings
Table 10. Enhanced Serial Audio Interface Signals (Continued)
Signal Name Signal Type
HCKT
Input or output
PC5 Input, output, or
disconnected
State during
Reset
Signal Description
GPIO
disconnected
High Frequency Clock for Transmitter—When programmed
as an input, this signal provides a high frequency clock
source for the ESAI transmitter as an alternate to the DSP
core clock. When programmed as an output, this signal
can serve as a high frequency sample clock (e.g., for
external DACs) or as an additional system clock.
Port C5—When the ESAI is configured as GPIO, this
signal is individually programmable as input, output, or
internally disconnected.
The default state after reset is GPIO disconnected.
FSR
Input or output
This pin has an internal pull up resistor.
This input is 5 V tolerant.
GPIO
disconnected
Frame Sync for Receiver—This is the receiver frame sync
input/output signal. In the asynchronous mode (SYN=0),
the FSR pin operates as the frame sync input or output
used by all the enabled receivers. In the synchronous
mode (SYN=1), it operates as either the serial flag 1 pin
(TEBE=0), or as the transmitter external buffer enable
control (TEBE=1, RFSD=1).
PC1 Input, output, or
disconnected
When this pin is configured as serial flag pin, its direction is
determined by the RFSD bit in the RCCR register. When
configured as the output flag OF1, this pin will reflect the
value of the OF1 bit in the SAICR register, and the data in
the OF1 bit will show up at the pin synchronized to the
frame sync in normal mode or the slot in network mode.
When configured as the input flag IF1, the data value at
the pin will be stored in the IF1 bit in the SAISR register,
synchronized by the frame sync in normal mode or the slot
in network mode.
Port C1—When the ESAI is configured as GPIO, this
signal is individually programmable as input, output, or
internally disconnected.
The default state after reset is GPIO disconnected.
Internal Pull down resistor.
This input is 5 V tolerant.
Freescale Semiconductor
PRELIMINARY
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