PDF DS_K4D263238D Data sheet ( Hoja de datos )

Número de pieza	DS_K4D263238D
Descripción	1M x 32Bit x 4 Banks Double Data Rate Synchronous DRAM with Bi-directional Data Strobe and DLL
Fabricantes	Samsung semiconductor
Logotipo
Hay una vista previa y un enlace de descarga de DS_K4D263238D (archivo pdf) en la parte inferior de esta página. Total 18 Páginas
No Preview Available ! K4D263238D 128M DDR SDRAM 128Mbit DDR SDRAM 1M x 32Bit x 4 Banks Double Data Rate Synchronous DRAM with Bi-directional Data Strobe and DLL Revision 1.3 July 2002 -1- Rev. 1.3 (Jul. 2002) 1 page K4D263238D 128M DDR SDRAM INPUT/OUTPUT FUNCTIONAL DESCRIPTION Symbol Type Function CK, CK1 Input The differential system clock Input. All of the inputs are sampled on the rising edge of the clock except DQ′s and DM′s that are sampled on both edges of the DQS. CKE Input Activates the CK signal when high and deactivates the CK signal when low. By deactivating the clock, CKE low indicates the Power down mode or Self refresh mode. CS Input CS enables the command decoder when low and disabled the com- mand decoder when high. When the command decoder is disabled, new commands are ignored but previous operations continue. RAS Input Latches row addresses on the positive going edge of the CK with RAS low. Enables row access & precharge. CAS Input Latches column addresses on the positive going edge of the CK with CAS low. Enables column access. WE Input Enables write operation and row precharge. Latches data in starting from CAS, WE active. DQS Input/Output Data input and output are synchronized with both edge of DQS. DM0 ~ DM3 Input Data In mask. Data In is masked by DM Latency=0 when DM is high in burst write. DM0 for DQ0 ~ DQ7, DM1 for DQ8 ~ DQ15, DM2 for DQ16 ~ DQ23, DM3 for DQ24 ~ DQ31. DQ0 ~ DQ31 Input/Output Data inputs/Outputs are multiplexed on the same pins. BA0, BA1 Input Selects which bank is to be active. A0 ~ A11 Input Row/Column addresses are multiplexed on the same pins. Row addresses : RA0 ~ RA11, Column addresses : CA0 ~ CA7. Column address CA8 is used for auto precharge. VDD/VSS Power Supply Power and ground for the input buffers and core logic. VDDQ/VSSQ Power Supply Isolated power supply and ground for the output buffers to provide improved noise immunity. VREF Power Supply Reference voltage for inputs, used for SSTL interface. MCL Must Connect Low Must connect Low 1 : The timing reference point for the differential clocking is the cross point of CK and CK. For any applications using the single ended clocking, apply VREF to CK pin. -5- Rev. 1.3 (Jul. 2002) 5 Page K4D263238D 128M DDR SDRAM DC CHARACTERISTICS Recommended operating conditions Unless Otherwise Noted, TA=0 to 65°C) Parameter Symbol Test Condition Operating Current (One Bank Active) ICC1 Precharge Standby Current in Power-down mode ICC2P Precharge Standby Current in Non Power-down mode ICC2N Active Standby Current power-down mode ICC3P Active Standby Current in in Non Power-down mode ICC3N Operating Current ( Burst Mode) ICC4 Refresh Current ICC5 Self Refresh Current ICC6 Note: 1. Measured with outputs open. 2. Refresh period is 32ms. Burst Lenth=2 tRC ≥ tRC(min) IOL=0mA, tCC= tCC(min) CKE ≤ VIL(max), tCC= tCC(min) CKE ≥ VIH(min), CS ≥ VIH(min), tCC= tCC(min). CKE ≤ VIL(max), tCC= tCC(min) CKE ≥ VIH(min), CS ≥ VIH(min), tCC= tCC(min) . IOL=0mA ,tCC= tCC(min), Page Burst, All Banks activated. tRC ≥ tRFC(min) CKE ≤ 0.2V -40 245 70 100 100 175 630 250 Version 3 -50 215 60 90 80 150 530 230 Unit Note mA 1 mA mA mA mA mA mA 2 mA AC INPUT OPERATING CONDITIONS Recommended operating conditions(Voltage referenced to VSS=0V, VDD/ VDDQ=2.5V+ 5%, TA=0 to 65°C) Parameter Input High (Logic 1) Voltage; DQ Symbol VIH Min VREF+0.35 Typ - Max - Unit V Note Input Low (Logic 0) Voltage; DQ VIL - - VREF-0.35 V Clock Input Differential Voltage; CK and CK VID 0.7 - VDDQ+0.6 V 1 Clock Input Crossing Point Voltage; CK and CK VIX 0.5VDDQ-0.2 - 0.5VDDQ+0.2 V 2 Note : 1. VID is the magnitude of the difference between the input level on CK and the input level on CK 2. The value of VIX is expected to equal 0.5*VDDQ of the transmitting device and must track variations in the DC level of the same - 11 - Rev. 1.3 (Jul. 2002) 11 Page

Páginas	Total 18 Páginas
PDF Descargar	[ Datasheet DS_K4D263238D.PDF ]

Hoja de datos destacado

Número de pieza	Descripción	Fabricantes
DS_K4D263238D	1M x 32Bit x 4 Banks Double Data Rate Synchronous DRAM with Bi-directional Data Strobe and DLL	Samsung semiconductor

Número de pieza	Descripción	Fabricantes
SLA6805M	High Voltage 3 phase Motor Driver IC.	Sanken
SDC1742	12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters.	Analog Devices

DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares,
permitiéndote verlos en linea o descargarlos en PDF.

DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar