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PDF DS_K4S161622D Data sheet ( Hoja de datos )
| Número de pieza | DS_K4S161622D | |
| Descripción | 1M x 16 SDRAM | |
| Fabricantes | Samsung semiconductor | |
| Logotipo |  |
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K4S161622D-TI/E
CMOS SDRAM
1M x 16 SDRAM
512K x 16bit x 2 Banks
Synchronous DRAM
LVTTL
Industrial/ExtendedTemperature
Revision 1.2
Jan 2003
Samsung Electronics reserves the right to change products or specification without notice.
Rev 1.2 Jan '03
1 page  
K4S161622D-TI/E
CMOS SDRAM
ABSOLUTE MAXIMUM RATINGS
Parameter
Voltage on any pin relative to Vss
Voltage on VDD supply relative to Vss
Storage temperature
Power dissipation
Short circuit current
Symbol
VIN, VOUT
VDD, VDDQ
TSTG
PD
IOS
Value
-1.0 ~ 4.6
-1.0 ~ 4.6
-55 ~ +150
1
50
Note : Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded.
Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
Unit
V
V
°C
W
mA
DC OPERATING CONDITIONS
Recommended operating conditions (Voltage referenced to VSS = 0V, Extended TA = -25 to +85°C , Industrial TA = -40 to +85°C)
Parameter
Symbol
Min
Typ
Max
Unit
Supply voltage
VDD, VDDQ
3.0
3.3
3.6
V
Input logic high votlage
VIH
2.0
3.0 VDDQ+0.3
V
Input logic low voltage
VIL -0.3 0 0.8 V
Output logic high voltage
VOH
2.4
-
-V
Output logic low voltage
VOL -
- 0.4 V
Input leakage current
ILI -10 - 10 uA
N: ote : 1. VIH (max) = 5.6V AC. The overshoot voltage duration is ≤ 3ns.
2. VIL (min) = -2.0V AC. The undershoot voltage duration is ≤ 3ns.
3. Any input 0V ≤ VIN ≤ VDDQ.
Input leakage currents include HI-Z output leakage for all bi-directional buffers with Tri-State outputs.
Note
1
2
IOH = -2mA
IOL = 2mA
3
CAPACITANCE (VDD = 3.3V, TA = 23°C, f = 1MHz, VREF =1.4V ± 200 mV)
Pin
Clock
RAS, CAS, WE, CS, CKE, L(U)DQM
Address
DQ0 ~ DQ15
Symbol
CCLK
CIN
CADD
COUT
Min
2
2
2
3
DECOUPLING CAPACITANCE GUIDE LINE
Recommended decoupling capacitance added to power line at board.
Parameter
Decoupling Capacitance between VDD and VSS
Decoupling Capacitance between VDDQ and VSSQ
Symbol
CDC1
CDC2
Note : 1. VDD and VDDQ pins are separated each other.
All VDD pins are connected in chip. All VDDQ pins are connected in chip.
2. VSS and VSSQ pins are separated each other
All VSS pins are connected in chip. All VSSQ pins are connected in chip.
Max
4
4
4
5
Value
0.1 + 0.01
0.1 + 0.01
Unit
pF
pF
pF
pF
Unit
uF
uF
Rev 1.2 Jan '03
5 Page 
K4S161622D-TI/E
CMOS SDRAM
BURST SEQUENCE (BURST LENGTH = 4)
Initial Address
A1 A0
Sequential
Interleave
0001230123
0112301032
1023012301
1130123210
BURST SEQUENCE (BURST LENGTH = 8)
Initial Address
A2 A1 A0
Sequential
Interleave
0 0 0 0 123 4 5 6 70 123 4 5 6 7
0 0 1 1 234 5 6 7 01 032 5 4 7 6
0 1 0 2 345 6 7 0 12 301 6 7 4 5
0 1 1 3 456 7 0 1 23 210 7 6 5 4
1 0 0 4 567 0 1 2 34 567 0 1 2 3
1 0 1 5 670 1 2 3 45 476 1 0 3 2
1 1 0 6 701 2 3 4 56 745 2 3 0 1
1 1 1 7 012 3 4 5 67 654 3 2 1 0
Rev 1.2 Jan '03
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet DS_K4S161622D.PDF ] | |
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