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DS_K7R323682M 데이터시트 PDF




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부품번호 DS_K7R323682M 기능
기능 1Mx36 & 2Mx18 & 4Mx9 QDRTM II b2 SRAM
제조업체 Samsung semiconductor
로고 Samsung semiconductor 로고


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DS_K7R323682M 데이터시트, 핀배열, 회로
K7R323682M
K7R321882M
K7R320982M
1Mx36 & 2Mx18 & 4Mx9 QDRTM II b2 SRAM
Document Title
1Mx36-bit, 2Mx18-bit, 4Mx9-bit QDRTM II b2 SRAM
Revision History
Rev. No.
History
0.0 1. Initial document.
0.1 1. Pin name change from DLL to Doff.
2. Vddq range change from 1.5V to 1.5V~1.8V.
3. Update JTAG test conditions.
4. Reserved pin for high density name change from NC to Vss/SA
5. Delete AC test condition about Clock Input timing Reference Level
6. Delete clock description on page 2 and add HSTL I/O comment
0.2 1. Update current characteristics in DC electrical characteristics
2. Change AC timing characteristics
3. Update JTAG instruction coding and diagrams
0.3 1. Add 4Mx9 Organization.
2. Add -FC25 part (Part Number, Idd, AC Characteristics)
3. Add AC electrical characteristics.
4. Change AC timing characteristics.
5. Change DC electrical characteristics(ISB1)
0.4 1. Change the data Setup/Hold time.
2. Change the Access Time.(tCHQV, tCHQX, etc.)
3. Change the Clock Cycle Time.(MAX value of tKHKH)
4. Change the JTAG instruction coding.
0.5 1. Change the Boundary scan exit order.
2. Change the AC timing characteristics(-25, -20)
3. Correct the Overshoot and Undershoot timing diagrams.
0.6 1. Change the JTAG Block diagram
0.7 1. Correct the JTAG ID register definition
2. Correct the AC timing parameter (delete the tKHKH Max value)
3. Change the Isb1 current.
0.8 1. Change the Maximum Clock cycle time.
2. Correct the 165FBGA package ball size.
1.0 1. Final spec release
2.0 1. Delete the x8 Org. Part
Draft Date
June, 30 2001
Dec. 5 2001
Remark
Advance
Preliminary
July, 29. 2002
Preliminary
Sep. 6. 2002
Preliminary
Oct. 7. 2002
Preliminary
Dec. 16, 2002
Preliminary
Dec. 26, 2002
Mar. 20, 2003
Preliminary
Preliminary
April. 4, 2003
Oct. 31, 2003
Dec. 1, 2003
Preliminary
Final
Final
The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the
specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions on the parameters of this device. If you have any ques-
tions, please contact the SAMSUNG branch office near your office, call or contact Headquarters.
- 1 - Dec. 2003
Rev 2.0




DS_K7R323682M pdf, 반도체, 판매, 대치품
K7R323682M
K7R321882M
K7R320982M
1Mx36 & 2Mx18 & 4Mx9 QDRTM II b2 SRAM
PIN CONFIGURATIONS(TOP VIEW) K7R321882M(2Mx18)
1 2 3 4 5 6 7 8 9 10 11
A C Q VSS/SA* SA W BW 1 K NC R S A VSS/SA* C Q
B NC Q9 D9 SA NC
K
BW0
SA
NC NC
Q8
C NC
NC
D10
VSS
SA
SA
SA VSS NC
Q7
D8
D NC
E NC
D11 Q10
VSS
VSS
VSS
VSS
VSS
NC
NC
Q11
VDDQ
VSS
VSS
VSS
V DDQ
NC
NC
D6
D7
Q6
F
NC
Q12
D12
VDDQ
VDD
VSS
VDD
V DDQ
NC
NC
Q5
G
NC
D13
Q13
VDDQ
VDD
VSS
VDD
V DDQ
NC
NC
D5
H
Doff
VREF
VDDQ
VDDQ
VDD
VSS
VDD
V DDQ
VDDQ
VREF
ZQ
J NC
NC
D14
VDDQ
VDD
VSS
VDD
V DDQ
NC
Q4
D4
K NC
NC
Q14
VDDQ
VDD
VSS
VDD
V DDQ
NC
D3
Q3
L
NC
Q15
D15
VDDQ
VSS
VSS
VSS
V DDQ
NC
NC
Q2
M NC
NC
D16
VSS
VSS
VSS
VSS
VSS
NC
Q1
D2
N
NC
D17 Q16
VSS
SA
SA
SA VSS NC NC
D1
P NC
NC Q17 SA
SA
C
SA SA NC D0 Q 0
R TDO TCK
SA
SA
SA
C
SA SA SA TMS TDI
Notes: 1. * Checked No Connect(NC) or Vss pins are reserved for higher density address, i.e. 10A for 72Mb and 2A for 144Mb.
2. BW0 controls write to D0:D8 and BW1 controls write to D9:D17.
PIN NAME
SYMBOL
K, K
C, C
CQ, CQ
Doff
SA
D0-17
PIN NUMBERS
6B, 6A
6P, 6R
11A, 1A
1H
3A,9A,4B,8B,5C-7C,5N-7N,4P,5P,7P,8P,3R-5R,7R-9R
10P,11N,11M,10K,11J,11G,10E,11D,11C,3B,3C,2D,
3F,2G,3J,3L,3M,2N
DESCRIPTION
Input Clock
Input Clock for Output Data
Output Echo Clock
DLL Disable when low
Address Inputs
Data Inputs
NOTE
1
Q0-17
11P,10M,11L,11K,10J,11F,11E,10C,11B,2B,3D,3E,
2F,3G,3K,2L,3N,3P
Data Outputs
W
R
B W0, BW1
VREF
ZQ
VDD
4A
8A
7B, 5A
2H,10H
11H
5F,7F,5G,7G,5H,7H,5J,7J,5K,7K
Write Control Pin,active when low
Read Control Pin,active when low
Block Write Control Pin,active when low
Input Reference Voltage
Output Driver Impedance Control Input
Power Supply ( 1.8 V )
2
VDDQ
4E,8E,4F,8F,4G,8G,3H,4H,8H,9H,4J,8J,4K,8K,4L,8L
Output Power Supply ( 1.5V or 1.8V )
V SS
TMS
TDI
TCK
TDO
NC
2A,10A,4C,8C,4D-8D,5E-7E,6F,6G,6H,6J,6K,5L-7L,4M-8M,4N,8N
10R
11R
2R
1R
7A,1B,5B,9B,10B,1C,2C,9C,1D,9D,10D,1E,2E,9E,1F,9F,
10F,1G,9G,10G,1J,2J,9J,1K,2K,9J,1L,9L,10L,1M,2M,
9M,1N,9N,10N,1P,2P,9P
Ground
JTAG Test Mode Select
JTAG Test Data Input
JTAG Test Clock
JTAG Test Data Output
No Connect
3
Notes: 1. C, C, K or K cannot be set to V R E F voltage.
2. When ZQ pin is directly connected to VDD output impedance is set to minimum value and it cannot be connected to ground or left unconnected.
3. Not connected to chip pad internally.
- 4 - Dec. 2003
Rev 2.0

4페이지










DS_K7R323682M 전자부품, 판매, 대치품
K7R323682M
K7R321882M
K7R320982M
1Mx36 & 2Mx18 & 4Mx9 QDRTM II b2 SRAM
Write Operations
Write cycles are initiated by activating W at the rising edge of the positive input clock K.
Address is presented and stored in the write address register synchronized with following K clock.
For 2-bit burst DDR operation, it will write two 36-bit or 18-bit or 9-bit or 8-bit data words with each write command.
The first "early" data is transfered and registered in to the device synchronous with same K clock rising edge with W presented.
Next burst data is transfered and registered synchronous with following K clock rising edge.
Continuous write operations are initated with K rising edge.
And "early writed" data is presented to the device on every rising edge of both K and K clocks.
When the W is disabled, the K7R323682M,K7R321882M and K7R320982M will enter into deselect mode.
The device disregards input data presented on the same cycle W disabled.
The K7R323682M, K7R321882M and K7R320982M support byte write operations.
With activating BW0 or BW1 ( BW2 or BW3 ) in write cycle, only one byte of input data is presented.
In K7R321882M, BW0 controls write operation to D0:D8, BW1 controls write operation to D9:D17.
And in K7R323682M BW2 controls write operation to D18:D26, BW 3 controls write operation to D27:D35.
And in K7R320982M BW controls write operation to D0:D8.
Programmable Impedance Output Buffer Operation
The designer can program the SRAM's output buffer impedance by terminating the ZQ pin to VSS through a precision resistor(RQ).
The value of RQ (within 15%) is five times the output impedance desired.
For example, 250resistor will give an output impedance of 50.
Impedance updates occur early in cycles that do not activate the outputs, such as deselect cycles.
In all cases impedance updates are transparent to the user and do not produce access time "push-outs" or other anomalous behav-
ior in the SRAM.
To guarantee optimum output driver impedance after power up, the SRAM needs 1024 non-read cycles.
Clock Consideration
K7R323682M,K7R321882M and K7R320982M utlizes internal DLL(Delay-Locked Loops) for maximum output
data valid window.
It can be placed into a stopped-clock state to minimize power with a modest restart time of 1024 clock cycles.
Circuitry automatically resets the DLL when absence of input clock is detected.
Single Clock Mode
K7R323682M,K7R321882M and K7R320982M can be operated with the single clock pair K and K,
insted of C or C for output clocks.
To operate these devices in single clock mode, C and C must be tied high during power up and must be maintained high
during operation.
After power up, this device can’t change to or from single clock mode.
System flight time and clock skew could not be compensated in this mode.
Depth Expansion
Separate input and output ports enables easy depth expansion.
Each port can be selected and deselected independently and read and write operation do not affect each other.
Before chip deselected, all read and write pending operations are completed.
Echo clock operation
To assure the output tracibility, the SRAM provides the output Echo clock, pair of compliment clock CQ and CQ,
which are synchronized with internal data output.
Echo clocks run free during normal operation.
The Echo clock is triggered by internal output clock signal, and transfered to external through same structures
as output driver.
- 7 - Dec. 2003
Rev 2.0

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DS_K7R323682M

1Mx36 & 2Mx18 & 4Mx9 QDRTM II b2 SRAM

Samsung semiconductor
Samsung semiconductor

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