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부품번호 | DS_M390S2858CT1 기능 |
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기능 | SDRAM DIMM | ||
제조업체 | Samsung semiconductor | ||
로고 | |||
M390S2858CT1
PC133 Registered DIMM
M390S2858CT1 SDRAM DIMM
128Mx72 SDRAM DIMM with PLL & Register based on Stacked 128Mx4, 4Banks 8K Ref., 3.3V SDRAMs with SPD
GENERAL DESCRIPTION
The Samsung M390S2858CT1 is a 128M bit x 72 Synchro-
nous Dynamic RAM high density memory module. The Sam-
sung M390S2858CT1 consists of eighteen CMOS Stacked
128Mx4 bit Synchronous DRAMs in two TSOP-II 400mil pack-
ages, three 18-bits Drive ICs for input control signal, one PLL
in 24-pin TSSOP package for clock and one 2K EEPROM in 8-
pin TSSOP package for Serial Presence Detect on a 168-pin
glass-epoxy substrate. Two 0.22uF and one 0.0022uF decou-
pling capacitors are mounted on the printed circuit board in
parallel for each SDRAM. The M390S2858CT1 is a Dual In-
line Memory Module and is intented for mounting into 168-pin
edge connector sockets.
Synchronous design allows precise cycle control with the use
of system clock. I/O transactions are possible on every clock
cycle. Range of operating frequencies, programmable laten-
cies allows the same device to be useful for a variety of high
bandwidth, high performance memory system applications.
FEATURE
• Performance range
Part No.
M390S2858CT1-C7C
M390S2858CT1-C7A
Max Freq. (Speed)
133MHz(7.5ns @ CL=2)
133MHz (7.5ns @ CL=3)
• Burst mode operation
• Auto & self refresh capability (8192 Cycles/64ms)
• LVTTL compatible inputs and outputs
• Single 3.3V ± 0.3V power supply
• MRS cycle with address key programs
Latency (Access from column address)
Burst length (1, 2, 4 , 8 & Full page)
Data scramble (Sequential & Interleave)
• All inputs are sampled at the positive going edge of the
system clock
• Serial presence detect with EEPROM
• PCB : Height (1,700mil), double sided component
PIN CONFIGURATIONS (Front side/back side)
PIN NAMES
Pin Front Pin Front Pin Front Pin Back Pin Back Pin Back
Pin Name
Function
1 VSS 29 DQM1 57 DQ18 85 VSS 113 DQM5 141 DQ50
2 DQ0 30 CS0 58 DQ19 86 DQ32 114 CS1 142 DQ51
A0 ~ A12
BA0 ~ BA1
Address input (Multiplexed)
Select bank
3 DQ1 31 DU 59 VDD 87 DQ33 115 RAS 143 VDD
DQ0 ~ DQ63 Data input/output
4 DQ2 32 VSS 60 DQ20 88 DQ34 116 VSS 144 DQ52
5 DQ3 33 A0 61 NC 89 DQ35 117 A1 145 NC
6 VDD 34 A2 62 *VREF 90 VDD 118 A3 146 *VREF
7 DQ4 35 A4 63 *CKE1 91 DQ36 119 A5 147 REGE
CB0 ~ CB7
CLK0
CKE0
Check bit (Data-in/data-out)
Clock input
Clock enable input
8 DQ5 36 A6 64 VSS 92 DQ37 120 A7 148 VSS
CS0 ~ CS3 Chip select input
9 DQ6 37 A8 65 DQ21 93 DQ38 121 A9 149 DQ53
10 DQ7 38 A10/AP 66 DQ22 94 DQ39 122 BA0 150 DQ54
11 DQ8 39 BA1 67 DQ23 95 DQ40 123 A11 151 DQ55
RAS
CAS
Row address strobe
Colume address strobe
12 VSS 40 VDD 68 VSS 96 VSS 124 VDD 152 VSS
WE
Write enable
13 DQ9 41 VDD 69 DQ24 97 DQ41 125 *CLK1 153 DQ56
14 DQ10 42 CLK0 70 DQ25 98 DQ42 126 A12 154 DQ57
15 DQ11 43 VSS 71 DQ26 99 DQ43 127 VSS 155 DQ58
16 DQ12 44 DU 72 DQ27 100 DQ44 128 CKE0 156 DQ59
DQM0 ~ 7
VDD
VSS
DQM
Power supply (3.3V)
Ground
17 DQ13 45 CS2 73 VDD 101 DQ45 129 CS3 157 VDD
*VREF
Power supply for reference
18 VDD 46 DQM2 74 DQ28 102 VDD 130 DQM6 158 DQ60
19 DQ14 47 DQM3 75 DQ29 103 DQ46 131 DQM7 159 DQ61
20 DQ15 48 DU 76 DQ30 104 DQ47 132 *A13 160 DQ62
REGE
SDA
Register enable
Serial data I/O
21 CB0 49 VDD 77 DQ31 105 CB4 133 VDD 161 DQ63
SCL
Serial clock
22 CB1 50 NC 78 VSS 106 CB5 134 NC 162 VSS
23 VSS 51 NC 79 *CLK2 107 VSS 135 NC 163 *CLK3
24 NC 52 CB2 80 NC 108 NC 136 CB6 164 NC
25 NC 53 CB3 81 *WP 109 NC 137 CB7 165 **SA0
SA0 ~ 2
DU
NC
Address in EEPROM
Don′t use
No connection
26 VDD 54 VSS 82 **SDA 110 VDD 138 VSS 166 **SA1
*WP
Write protection
27 WE 55 DQ16 83 **SCL 111 CAS 139 DQ48 167 **SA2
28 DQM0 56 DQ17 84 VDD 112 DQM4 140 DQ49 168 VDD
* These pins are not used in this module.
** These pins should be NC in the system
which does not support SPD.
SAMSUNG ELECTRONICS CO., Ltd. reserves the right to change products and specifications without notice.
REV. 0.1 Sept. 2001
M390S2858CT1
PC133 Registered DIMM
STANDARD TIMING DIAGRAM WITH PLL & REGISTER (CL=2, BL=4)
*1. Register Input
0
CLK
1
23
*2
*1
Control Signal(RAS,CAS,WE)
REG
*3 DOUT
4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
RAS
CAS
WE
*2. Register Output
RAS
CAS
td
WE
*3. SDRAM
DQ
tr
tRAC(refer to *1)
tRAC(refer to *2)
CAS latency(refer to *1)
=2CLK+1CLK
tSAC
Qa0 Qa1 Qa2 Qa3
CAS latency(refer to *2)
=2CLK
Row Active Read
Command
Precharge
Command
td tr
1CLK
Db0 Db1 Db2 Db3
tRDL
Row Active Write
Command
Precharge
Command
td, tr = Delay of register (74ALVCF162835)
Notes : 1. In case of module timing, command cycles delayed 1CLK with respect to external input timing at the address and input signal
because of the buffering in register (74ALVCF162835). Therefore, Input/Output signals of read/write function should be
issued 1CLK earlier as compared to Unbuffered DIMMs.
2. DIN is to be issued 1clock after write command in external timing because DIN is issued directly to module.
: Don′t care
REV. 0.1 Sept. 2001
4페이지 M390S2858CT1
PC133 Registered DIMM
AC OPERATING TEST CONDITIONS (VDD = 3.3V ± 0.3V, TA = 0 to 70°C)
Parameter
AC input levels (Vih/Vil)
Input timing measurement reference level
Input rise and fall time
Output timing measurement reference level
Output load condition
Value
2.4/0.4
1.4
tr/tf = 1/1
1.4
See Fig. 2
Unit
V
V
ns
V
3.3V
Vtt = 1.4V
Output
870Ω
1200Ω
50pF
VOH (DC) = 2.4V, IOH = -2mA
VOL (DC) = 0.4V, IOL = 2mA
Output
Z0 = 50Ω
50Ω
50pF
(Fig. 1) DC output load circuit
(Fig. 2) AC output load circuit
OPERATING AC PARAMETER
(AC operating conditions unless otherwise noted)
Parameter
Symbol
Row active to row active delay
RAS to CAS delay
Row precharge time
Row active time
Row cycle time
Last data in to row precharge
Last data in to Active delay
tRRD(min)
tRCD(min)
tRP(min)
tRAS(min)
tRAS(max)
tRC(min)
tRDL(min)
tDAL(min)
Version
-7C -7A
15 15
15 20
15 20
45 45
100
60 65
2
2 CLK + tRP
Unit Note
ns 1
ns 1
ns 1
ns 1
us
ns 1
CLK 2,5
-5
Last data in to new col. address delay
tCDL(min)
1
CLK 2
Last data in to burst stop
tBDL(min) 1 CLK 2
Col. address to col. address delay
tCCD(min)
1
CLK 3
Number of valid output data
CAS latency=3
2 ea 4
CAS latency=2
1
Notes :
1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time
and then rounding off to the next higher integer.
2. Minimum delay is required to complete write.
3. All parts allow every cycle column address change.
4. In case of row precharge interrupt, auto precharge and read burst stop.
5. In 100MHz and below 100MHz operating conditions, tRDL=1CLK and tDAL=1CLK + 20ns is also supported.
SAMSUNG recommends tRDL=2CLK and tDAL=2CLK + tRP.
REV. 0.1 Sept. 2001
7페이지 | |||
구 성 | 총 12 페이지수 | ||
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구매 문의 | 일반 IC 문의 : 샘플 및 소량 구매 ----------------------------------------------------------------------- IGBT, TR 모듈, SCR 및 다이오드 모듈을 포함한 광범위한 전력 반도체를 판매합니다. 전력 반도체 전문업체 상호 : 아이지 인터내셔날 사이트 방문 : [ 홈페이지 ] [ 블로그 1 ] [ 블로그 2 ] |
부품번호 | 상세설명 및 기능 | 제조사 |
DS_M390S2858CT1 | SDRAM DIMM | Samsung semiconductor |
DS_M390S2858CT1 | SDRAM DIMM | Samsung semiconductor |
DataSheet.kr | 2020 | 연락처 | 링크모음 | 검색 | 사이트맵 |