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DT70V27S PDF 데이터시트 : 부품 기능 및 핀배열

부품번호 DT70V27S
기능 HIGH-SPEED 3.3V 32K x 16 DUAL-PORT STATIC RAM
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DT70V27S 데이터시트, 핀배열, 회로
HIGH-SPEED 3.3V
32K x 16 DUAL-PORT
STATIC RAM
IDT70V27S/L
Features:
x True Dual-Ported memory cells which allow simultaneous
access of the same memory location
x High-speed access
– Industrial: 35ns (max.)
– Commercial: 15/20/25/35/55ns (max.)
x Low-power operation
– IDT70V27S
Active: 500mW (typ.)
Standby: 3.3mW (typ.)
– IDT70V27L
Active: 500mW (typ.)
Standby: 660µW (typ.)
x Separate upper-byte and lower-byte control for bus
matching capability
x Dual chip enables allow for depth expansion without
external logic
Functional Block Diagram
R/WL
UBL
CE0L
CE1L
OEL
LBL
x IDT70V27 easily expands data bus width to 32 bits or more
using the Master/Slave select when cascading more than
one device
x M/S = VIH for BUSY output flag on Master,
M/S = VIL for BUSY input on Slave
x Busy and Interrupt Flags
x On-chip port arbitration logic
x Full on-chip hardware support of semaphore signaling
between ports
x Fully asynchronous operation from either port
x LVTTL-compatible, single 3.3V (±0.3V) power supply
x Available in 100-pin Thin Quad Flatpack (TQFP), 108-pin
Ceramic Pin Grid Array (PGA), and 144-pin Fine Pitch BGA
(fpBGA)
x Industrial temperature range (-40°C to +85°C) is available
for selected speeds
R/WR
UBR
CE0R
CE1R
OER
LBR
I/O8-15L
I/O0-7L
BUSYL (1,2)
I/O
Control
I/O
Control
A14L
A0L
Address
Decoder
A14L
A0L
CE0L
CE1L
OEL
R/WL
32Kx16
MEMORY
ARRAY
70V27
ARBITRATION
INTERRUPT
SEMAPHORE
LOGIC
SEM L
NOTES:
INT
(2)
L
M/S (2)
1) BUSY is an input as a Slave (M/S=VIL) and an output as a Master (M/S=VIH).
2) BUSY and INT are non-tri-state totem-pole outputs (push-pull).
©2000 Integrated Device Technology, Inc.
6.011
Address
Decoder
A14R
A0R
CE0R
CE1R
OER
R/WR
I/O8-15R
I/O0-7R
BUSYR(1,2)
A14R
A0R
SEMR
INTR(2)
3603 drw 01
JANUARY 2001
DSC 3603/7




DT70V27S pdf, 반도체, 판매, 대치품
IDT 70V27S/L
High-Speed 3.3V 32K x 16 Dual-Port Static RAM
Commercial and Industrial Temperature Range
Pin Configurations(1,2,3) (con't.)
81 80 77 74 72 69 68 65 63 60 57 54
12 A10R A11R A14R NC UBR SEMR GND GND NC I/O13R I/O10R NC
84 83 78 76 73 70 67 64 61 59 56 53
11 A7R A8R A13R NC LBR CE1R R/WR GND I/O14R I/O12R I/O9R NC
87 86 82 79 75 71 66 62 58 55 51 50
10 A4R A5R A9R A12R NC CE0R OER I/O15R I/O11R NC I/O8R I/O7R
90 88 85
09 A1R A3R A6R
52 49 47
NC Vcc I/O5R
92 91 89
08 INTR A0R A2R
48 46 45
I/O6R I/O4R I/O3R
95 94 93
07 GND M/S BUSYR
96 97 98
06 BUSYL INTL NC
99 100 102
05 A0L A1L A3L
IDT70V27G
G108-1(4)
108-PIN PGA
TOP VIEW(5)
44 43 42
I/O2R I/O1R I/O0R
39 40 41
I/O1L I/O0L GND
35 37 38
I/O4L I/O2L GND
101 103 106
04 A2L A4L A7L
31 34 36
Vcc I/O5L I/O3L
104 105 1 4 8 12 17 21 25 28 32 33
03 A5L A6L A10L A13L NC CE1L GND I/O14L I/O10L NC I/O7L I/O6L
107 2 5 7 10 13 16 19 22 24 29 30
02 A8L A11L A14L NC UBL SEML OEL GND I/O13L I/O11L NC I/O8L
108 3 6 9 11 14 15 18 20 23 26 27
01 A9L A12L NC LBL CE0L Vcc R/WL NC I/O15L I/O12L I/O9L NC
AB CDE
INDEX
NOTES:
1. All VCC pins must be connected to power supply.
2. All GND pins must be connected to ground supply.
3. Package body is approximately 1.21in x 1.21in x .16in.
4. This package code is used to reference the package diagram.
5. This text does not indicate orientation of the actual part-marking.
FGHJ K L M
3603 drw 03
Pin Names
Left Port
Right Port
CE0L, CE1L
R/WL
CE0R, CE1R
R/WR
OEL OER
A0L - A14L
A0R - A14R
I/O0L - I/O15L
I/O0R - I/O15R
SEML
SEMR
UBL UBR
LBL LBR
INTL INTR
BUSYL
BUSYR
M/S
VCC
GND
4
Names
Chip Enable
Read/Write Enable
Output Enable
Address
Data Input/Output
Semaphore Enable
Upper Byte Select
Lower Byte Select
Interrupt Flag
Busy Flag
Master or Slave Select
Power
Ground
3603 tbl 01

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DT70V27S 전자부품, 판매, 대치품
IDT 70V27S/L
High-Speed 3.3V 32K x 16 Dual-Port Static RAM
Commercial and Industrial Temperature Range
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range(1,6,7) (VCC = 3.3V ± 0.3V)
70V27X15
Com'l Only
70V27X20
Com'l Only
70V27X25
Com'l Only
Symbol
Parameter
Test Condition
Version
Typ.(2) Max. Typ.(2) Max. Typ.(2) Max. Unit
ICC Dynamic Operating
Current
(Both Ports Active)
CE = VIL, Outputs Disabled
SEM = VIH
f = fMAX(3)
COM'L S 170 260 165 255 145 245 mA
L 170 225 165 220 145 210
IND'L
S ____
____
____
____
145 280
L ____ ____ ____ ____ 145 245
ISB1 Standby Current
CEL = CER = VIH
(Bo th Ports - TTL Level SEMR = SEML = VIH
Inputs)
f = fMAX(3)
COM'L S 44 70 39 60 27 50 mA
L 44 60 39 50 27 40
IND'L
S ____
____
____
____
27
60
L ____ ____ ____ ____ 27 50
ISB2 Standby Current
CE"A" = VIL and CE"B" = VIH(5)
COM'L S 115
160 105 155
90
150 mA
(One Port - TTL Level Active Port Outputs Disabled,
L 115 145 105 140 90 135
Inputs)
f=fMAX(3)
SEMR = SEML = VIH
IND'L
S ____
____
____
____
90 170
L ____ ____ ____ ____ 90 150
ISB3 Full Standby Current
(Both Ports - All
CMOS Level Inputs)
Both Ports CEL and
CER > VCC - 0.2V
VIN > VCC - 0.2V or
VIN < 0.2V, f = 0(4)
SEMR = SEML > VCC - 0.2V
COM'L S 1.0 6 1.0 6 1.0 6 mA
L 0.2 3 0.2 3 0.2 3
IND'L
S ____
____
____
____
1.0
10
L ____ ____ ____ ____ 0.2
6
ISB4 Full Standby Current CE"A" < 0.2V and
(One Port - All CMOS CE"B" > VCC - 0.2V(5)
COM'L S 115 155 105 150 90 145 mA
L 115 140 105 135 90 130
Level Inputs)
SEMR = SEML > VCC - 0.2V
VIN > VCC - 0.2V or VIN < 0.2V
IND'L
S ____
____
____
____
90 170
Active Port Outputs Disabled
L ____ ____ ____ ____ 90 145
f = fMAX(3)
NOTES:
3603 tbl 10a
1. 'X' in part numbers indicates power rating (S or L).
2. VCC = 3.3V, TA = +25°C, and are not production tested. ICCDC = 90mA (Typ.)
3. At f = fMAX, address and control lines (except Output Enable) are cycling at the maximum frequency read cycle of 1/tRC, and using AC Test Conditionsof input
levels of GND to 3V.
4. f = 0 means no address or control lines change.
5. Port "A" may be either left or right port. Port "B" is the opposite from port "A".
6. Refer to Chip Enable Truth Table.
7. Industrial temperature: for other speeds, packages and powers contact your sales office.
7

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