Datasheet.kr   

DT72V3664L15PF PDF 데이터시트 : 부품 기능 및 핀배열

부품번호 DT72V3664L15PF
기능 3.3 VOLT CMOS SyncBiFIFOTM WITH BUS-MATCHING 2/048 x 36 x 2 4/096 x 36 x 2 8/192 x 36 x 2
제조업체 Integrated Device Technology
로고 Integrated Device Technology 로고 



전체 30 페이지

		

No Preview Available !

DT72V3664L15PF 데이터시트, 핀배열, 회로
3.3 VOLT CMOS SyncBiFIFOTM WITH BUS-MATCHING
2,048 x 36 x 2
4,096 x 36 x 2
8,192 x 36 x 2
IDT72V3654
IDT72V3664
IDT72V3674
FEATURES
Memory storage capacity:
IDT72V3654 – 2,048 x 36 x 2
IDT72V3664 – 4,096 x 36 x 2
IDT72V3674 – 8,192 x 36 x 2
Clock frequencies up to 100 MHz (6.5ns access time)
Two independent clocked FIFOs buffering data in opposite
directions
Select IDT Standard timing (using EFA, EFB, FFA, and FFB flags
functions) or First Word Fall Through Timing (using ORA, ORB,
IRA, and IRB flag functions)
Programmable Almost-Empty and Almost-Full flags; each has five
default offsets (8, 16, 64, 256 and 1,024 )
Serial or parallel programming of partial flags
Port B bus sizing of 36 bits (long word), 18 bits (word) and 9 bits
(byte)
Big- or Little-Endian format for word and byte bus sizes
Retransmit Capability
Master Reset clears data and configures FIFO, Partial Reset
clears data but retains configuration settings
Mailbox bypass registers for each FIFO
Free-running CLKA and CLKB may be asynchronous or coincident
(simultaneous reading and writing of data on a single clock edge
is permitted)
Auto power down minimizes power dissipation
Available in space saving 128-pin Thin Quad Flatpack (TQFP)
Pin and functionally compatible version of the 5V operating
IDT723654/723664/723674
Pin compatible to the lower density parts, IDT72V3624/72V3634/
72V3644
Industrial temperature range (–40°C to +85°C) is available
FUNCTIONAL BLOCK DIAGRAM
CLKA
CSA
W/RA
ENA
MBA
MRS1
PRS1
FFA/IRA
AFA
Port-A
Control
Logic
FIFO1,
Mail1
Reset
Logic
36
Mail 1
Register
36
RAM ARRAY
2,048 x 36
36
4,096 x 36
8,192 x 36
FIFO1
Write
Pointer
Read
Pointer
Status Flag
Logic
MBF1
36
EFB/ORB
AEB
FS2
FS0/SD
FS1/SEN
A0-A35
EFA/ORA
AEA
Programmable Flag
Offset Registers
Timing
Mode
13
FIFO2
Status Flag
Logic
FWFT
B0-B35
FFB/IRB
AFB
RT1
RTM
RT2
36
FIFO1 and
FIFO2
Retransmit
Logic
MBF2
Read
Pointer
Write
Pointer
RAM ARRAY
36 2,048 x 36
4,096 x 36
8,192 x 36
Mail 2
Register
36
36
FIFO2,
Mail2
Reset
Logic
MRS2
PRS2
Port-B
Control
Logic
CLKB
CSB
W/RB
ENB
MBB
BE
BM
SIZE
4664 drw01
IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc. The SyncFIFO is a trademark of Integrated Device Technology, Inc.
COMMERCIAL TEMPERATURE RANGE
1
2003 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.
NOVEMBER 2003
DSC-4664/4




DT72V3664L15PF pdf, 반도체, 판매, 대치품
IDT72V3654/72V3664/72V3674 3.3V CMOS SyncBiFIFOTM WITH BUS-MATCHING
2,048 x 36 x 2, 4,096 x 36 x 2 and 8,192 x 36 x 2
COMMERCIALTEMPERATURERANGE
PIN DESCRIPTIONS
Symbol
Name
I/O
Description
A0-A35 Port A Data
I/O 36-bit bidirectional data port for side A.
AEA PortAAlmost-
Empty Flag
AEB PortBAlmost-
Empty Flag
AFA PortAAlmost-
Full Flag
AFB PortBAlmost-
Full Flag
O Programmable Almost-Empty flag synchronized to CLKA. It is LOW when the number of words in
FIFO2 is less than or equal to the value in the Almost-Empty A Offset register, X2.
O Programmable Almost-Empty flag synchronized to CLKB. It is LOW when the number of words in
FIFO1 is less than or equal to the value in the Almost-Empty B Offset register, X1.
O Programmable Almost-Full flag synchronized to CLKA. It is LOW when the number of empty
locations in FIFO1 is less than or equal to the value in the Almost-Full A Offset register, Y1.
O Programmable Almost-Full flag synchronized to CLKB. It is LOW when the number of empty
locations in FIFO2 is less than or equal to the value in the Almost-Full B Offset register, Y2.
B0-B35
BE/FWFT
Port A Data
Big-Endian/
First Word
Fall Through
Select
I/O 36-bit bidirectional data port for side B.
I This is a dual purpose pin. During Master Reset, a HIGH on BE will select Big Endian operation.
In this case, depending on the bus size, the most significant byte or word on Port A is read from
Port B first (A-to-B data flow) or written to Port B first (B-to-A data flow). A LOW on BE will select
Little-Endian operation. In this case, the least significant byte or word on Port A is read from Port B
first (for A-to-B data flow) or written to Port B first (B-to-A data flow). After Master Reset, this pin
selects the timing mode. A HIGH on FWFT selects IDT Standard mode, a LOW selects First Word
Fall Through mode. Once the timing mode has been selected, the level on FWFTmust be static
throughout device operation.
BM(1) Bus-MatchSelect I A HIGH on this pin enables either byte or word bus width on Port B, depending on the state of
(Port B)
SIZE. A LOW selects long word operation. BM works with SIZE and BE to select the bus size and
endian arrangement for Port B. The level of BM must be static throughout device operation.
CLKA
Port A Clock
I CLKA is a continuous clock that synchronizes all data transfers through Port A and can be
asynchronous or coincident to CLKB. FFA/IRA, EFA/ORA, AFA, and AEA are all synchronized
to the LOW-to-HIGH transition of CLKA.
CLKB
Port B Clock
I CLKB is a continuous clock that synchronizes all data transfers through Port B and can be
asynchronous or coincident to CLKA. FFB/IRB, EFB/ORB, AFB, and AEBare synchronized to
the LOW-to-HIGH transition of CLKB.
CSA Port A Chip Select I CSA must be LOW to enable to LOW-to-HIGH transition of CLKA to read or write on Port A.
The A0-A35 outputs are in the high-impedance state when CSAis HIGH.
CSB
Port B Chip Select
I CSB must be LOW to enable a LOW-to-HIGH transition of CLKB to read or write data on Port B.
The B0-B35 outputs are in the high-impedance state when CSBis HIGH.
EFA/ORA Port A Empty/
O This is a dual function pin. In the IDT Standard mode, the EFA function is selected. EFA
Output Ready Flag
indicates whether or not the FIFO2 memory is empty. In the FWFT mode, the ORA function is
selected. ORA indicates the presence of valid data on A0-A35 outputs, available for reading.
EFA/ORA is synchronized to the LOW-to-HIGH transition of CLKA.
EFB/ORB Port B Empty/
O This is a dual function pin. In the IDT Standard mode, the EFBfunction is selected. EFBindicates
Output Ready Flag
whether or not the FIFO1 memory is empty. In the FWFT mode, the ORB function is selected. ORB
indicates the presence of valid data on the B0-B35 outputs, available for reading. EFB/ORB is
synchronized to the LOW-to-HIGH transition of CLKB.
ENA Port A Enable
I ENA must be HIGH to enable a LOW-to-HIGH transition of CLKA to read or write data on Port A.
ENB Port B Enable
I ENB must be HIGH to enable a LOW-to-HIGH transition of CLKB to read or write data on Port B.
FFA/IRA
Port A Full/
Input Ready Flag
FFB/IRB
Port B Full/
Input Ready Flag
O This is a dual function pin. In the IDT Standard mode, the FFA function is selected. FFA indicates
whether or not the FIFO1 memory is full. In the FWFT mode, the IRA function is selected. IRA
indicates whether or not there is space available for writing to the FIFO1 memory. FFA/IRA is
synchronized to the LOW-to-HIGH transition of CLKA.
O This is a dual function pin. In the IDT Standard mode, the FFBfunction is selected. FFBindicates
whether or not the FIFO2 memory is full. In the FWFT mode, the IRB function is selected. IRB
indicates whether or not there is space available for writing to the FIFO2 memory. FFB/IRB is
synchronized to the LOW-to-HIGH transition of CLKB.
4

4페이지










DT72V3664L15PF 전자부품, 판매, 대치품
IDT72V3654/72V3664/72V3674 3.3V CMOS SyncBiFIFOTM WITH BUS-MATCHING
2,048 x 36 x 2, 4,096 x 36 x 2 and 8,192 x 36 x 2
COMMERCIALTEMPERATURERANGE
ABSOLUTE MAXIMUM RATINGS OVER OPERATING FREE-AIR
TEMPERATURE RANGE (Unless otherwise noted)(1)
Symbol
Rating
Commercial
Unit
VCC Supply Voltage Range
–0.5 to +4.6
V
VI(2) Input Voltage Range
–0.5 to VCC+0.5
V
VO(2) Output Voltage Range
–0.5 to VCC+0.5
V
IIK Input Clamp Current (VI < 0 or VI > VCC)
±20 mA
IOK Output Clamp Current (VO = < 0 or VO > VCC)
±50 mA
IOUT Continuous Output Current (VO = 0 to VCC)
±50 mA
ICC Continuous Current Through VCC or GND
±400 mA
TSTG
Storage Temperature Range
–65 to 150
°C
NOTES:
1. Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these
or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect
device reliability.
2. The input and output voltage ratings may be exceeded provided the input and output current ratings are observed.
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Min. Typ. Max. Unit
VCC(1) Supply Voltage for 10ns
3.15 3.3 3.45 V
VCC Supply Voltage for 15ns
3.0 3.3 3.6 V
VIH High-Level Input Voltage
2 — VCC+0.5 V
VIL Low-Level Input Voltage
——
0.8 V
IOH High-Level Output Current
——
–4 mA
IOL Low-Level Output Current
——
8 mA
TA OperatingTemperature
0—
70 °C
NOTE:
1. For 10ns speed grade: Vcc = 3.3V ± 0.15V, JEDEC JESD8-A compliant
ELECTRICAL CHARACTERISTICS OVER RECOMMENDED OPERATING FREE-
AIR TEMPERATURE RANGE (Unless otherwise noted)
Symbol
Parameter
Test Conditions
VOH
VOL
ILI
ILO
ICC2(3)
ICC3(3)
CIN(4)
COUT(4)
Output Logic "1" Voltage
Output Logic "0" Voltage
Input Leakage Current (Any Input)
Output Leakage Current
Standby Current (with CLKA & CLKB running)
Standby Current (no clocks running)
Input Capacitance
Output Capacitance
VCC = 3.0V,
VCC = 3.0V,
VCC = 3.6V,
VCC = 3.6V,
VCC = 3.6V,
VCC = 3.6V,
VI = 0,
VO = 0,
IOH = –4 mA
IOL = 8 mA
VI = VCC or 0
VO = VCC or 0
VI = VCC –0.2V or 0V
VI = VCC –0.2V or 0V
f = 1 MHz
f = 1 MHZ
NOTES:
1. All typical values are at VCC = 3.3V, TA = 25°C.
2. Commercial-10ns speed grade only: Vcc = 3.3V ± 0.15V, TA = 0° to +70°; JEDEC JESD8-A compliant.
3. For additional ICC information, see Figure 1, Typical Characteristics: Supply Current (ICC) vs. Clock Frequency (fS).
4. Characterized values, not currently tested.
IDT72V3654
IDT72V3664
IDT72V3674
Commercial
tCLK = 10, 15 ns(2)
Min. Typ.(1) Max.
2.4 — —
— — 0.5
— — ±10
— — ±10
——
5
——
1
—4—
—8—
Unit
V
V
µA
µA
mA
mA
pF
pF
7

7페이지



구       성총 30 페이지
다운로드[ DT72V3664L15PF.PDF 데이터시트 ]
구매 문의
일반 IC 문의 : 샘플 및 소량 구매
-----------------------------------------------------------------------

전력 반도체 판매 ( IGBT, TR 모듈, SCR, 다이오드 모듈 )

휴대전화 : 010-3582-2743


상호 : 아이지 인터내셔날

전화번호 : 051-319-2877, [ 홈페이지 ]



링크공유

링크 :

관련 데이터시트

부품번호상세설명 및 기능제조사
DT72V3664L15PF

3.3 VOLT CMOS SyncBiFIFOTM WITH BUS-MATCHING 2/048 x 36 x 2 4/096 x 36 x 2 8/192 x 36 x 2

Integrated Device Technology
Integrated Device Technology

DataSheet.kr    |   2019   |  연락처   |  링크모음   |   검색  |   사이트맵