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74ACT16373 데이터시트 PDF




Fairchild Semiconductor에서 제조한 전자 부품 74ACT16373은 전자 산업 및 응용 분야에서
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부품번호 74ACT16373 기능
기능 16-Bit Transparent Latch with 3-STATE Outputs
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74ACT16373 데이터시트, 핀배열, 회로
August 1999
Revised October 1999
74ACT16373
16-Bit Transparent Latch with 3-STATE Outputs
General Description
The ACT16373 contains sixteen non-inverting latches with
3-STATE outputs and is intended for bus oriented applica-
tions. The device is byte controlled. The flip-flops appear
transparent to the data when the Latch Enable (LE) is
HIGH. When LE is low, the data that meets the setup time
is latched. Data appears on the bus when the Output
Enable (OE) is LOW. When OE is HIGH, the outputs are in
high Z state.
Features
s Separate control logic for each byte
s 16-bit version of the ACT373
s Outputs source/sink 24 mA
s TTL-compatible inputs
Ordering Code:
Order Number Package Number
Package Description
74ACT16373MEA
MS48A
48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300” Wide
74ACT16373MTD
MTD48
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Logic Symbol
Connection Diagram
Pin Descriptions
Pin Names
OEn
LEn
I0–I15
O0–O15
Description
Output Enable Input (Active Low)
Latch Enable Input
Inputs
Outputs
FACTis a trademark of Fairchild Semiconductor Corporation.
© 1999 Fairchild Semiconductor Corporation DS500297
www.fairchildsemi.com




74ACT16373 pdf, 반도체, 판매, 대치품
AC Electrical Characteristics
Symbol
Parameter
tPLH Propagation Delay
tPHL
Dn to On
tPLH Propagation Delay
tPHL LE to On
tPZH Output Enable
tPZL Delay
tPHZ Output Disable
tPLZ Delay
Note 4: Voltage Range 5.0 is 5.0V ± 0.5V.
VCC
(V)
(Note 4)
5.0
5.0
5.0
5.0
Min
3.1
2.6
3.1
2.8
2.5
2.7
2.1
2.0
AC Operating Requirements
Symbol
Parameter
tS Setup Time, HIGH or
LOW, Input to Clock
tH Hold time, HIGH or
LOW, Input to Clock
tW CS Pulse Width,
HIGH or LOW
Note 5: Voltage Range 5.0 is 5.0V ± 0.5V
VCC
(V)
(Note 5)
5.0
5.0
5.0
Capacitance
TA = +25°C
CL = 50 pF
Typ
5.3
4.6
5.4
4.9
4.7
4.8
5.1
4.5
Max
7.9
7.3
7.9
7.3
7.4
7.5
7.9
7.4
TA = −40°C to +85°C
CL = 50 pF
Min Max
3.1 8.4
2.6 7.8
3.2 8.4
2.8 7.8
2.5 7.9
2.7 8.0
2.1 8.2
2.0 7.9
Units
ns
ns
ns
ns
TA = +25°C
TA = −40°C to +85°C
CL = 50 pF
CL = 50 pF
Guaranteed Minimum
3.0 3.0
1.5 1.5
4.0 4.0
Units
ns
ns
ns
Symbol
CIN
CPD
Parameter
Input Capacitance
Power Dissipation Capacitance
Typ Units
Conditions
4.5 pF VCC = 5.0V
30 pF VCC = 5.0V
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74ACT16373 전자부품, 판매, 대치품
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
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