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부품번호 | 74ACT18823MTD 기능 |
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기능 | 18-Bit D-Type Flip-Flop with 3-STATE Outputs | ||
제조업체 | Fairchild Semiconductor | ||
로고 | |||
전체 6 페이지수
August 1999
Revised October 1999
74ACT18823
18-Bit D-Type Flip-Flop with 3-STATE Outputs
General Description
The ACT18823 contains eighteen non-inverting D-type flip-
flops with 3-STATE outputs and is intended for bus oriented
applications. The device is byte controlled. A buffered clock
(CP), Clear (CLR), Clock Enable (EN) and Output Enable
(OE) are common to each byte and can be shorted
together for full 18-bit operation.
Features
s Broadside pinout allows for easy board layout
s Separate control logic for each byte
s Extra data width for wider address/data paths or buses
carrying parity
s Outputs source/sink 24 mA
s TTL-compatible inputs
Ordering Code:
Order Number Package Number
Package Description
74ACT18823SSC
MS56A
56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300” Wide
74ACT18823MTD
MTD56
56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Logic Symbol
Connection Diagram
Pin Descriptions
Pin Names
OEn
CLRn
ENn
CPn
I0–I17
O0–O17
Description
Output Enable Input (Active LOW)
Clear (Active LOW)
Clock Enable (Active LOW)
Clock Pulse Input
Inputs
Outputs
FACT™ is a trademark of Fairchild Semiconductor Corporation.
© 1999 Fairchild Semiconductor Corporation DS500294
www.fairchildsemi.com
AC Electrical Characteristics
Symbol
Parameter
fMAX
Maximum Clock
Frequency
tPHL Propagation Delay
tPLH
CPn to On
tPHL Propagation Delay
CLRn to On
tPZL Output Enable Time
tPZH
tPLZ Output Disable Time
tPHZ
Note 5: Voltage Range 5.0 is 5.0V ± 0.5V.
AC Operating Requirements
VCC
(V)
(Note 5)
5.0
5.0
5.0
5.0
5.0
TA = +25°C
CL = 50 pF
Min Max
100
2.0 9.0
2.0 9.0
2.0 9.0
2.0 9.0
2.0 9.0
1.5 7.0
1.5 8.0
TA = −40°C to +85°C
CL = 50 pF
Min Max
90
2.0 9.5
2.0 9.5
2.0 9.5
2.0 10.0
2.0 10.0
1.5 7.5
1.5 8.5
Symbol
Parameter
tS Setup Time, HIGH or LOW,
Input to Clock
tH Hold Time, HIGH or LOW,
Input to Clock
tS Setup Time, HIGH or LOW,
Enable to Clock
tH Hold Time, HIGH or LOW,
Enable to Clock
tW CPn Pulse Width,
HIGH or LOW
tW CLRn Pulse Width,
HIGH or LOW
trec Recovery Time,
CLRn to CPn
Note 6: Voltage Range 5.0 is 5.0V ± 0.5V.
Capacitance
VCC
(V)
(Note 6)
5.0
5.0
5.0
5.0
5.0
5.0
5.0
TA = +25°C
TA = −40°C to +85°C
CL = 50 pF
CL = 50 pF
Guaranteed Minimum
3.0 3.0
1.5 1.5
3.0 3.0
1.5 1.5
4.0 4.0
4.0 4.0
6.0 6.0
Units
MHz
ns
ns
ns
ns
Units
ns
ns
ns
ns
ns
ns
ns
Symbol
CIN
CPD
Parameter
Input Pin Capacitance
Power Dissipation Capacitance
Typ Units
Conditions
4.5 pF VCC = 5.0V
95 pF VCC = 5.0V
www.fairchildsemi.com
4
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부품번호 | 상세설명 및 기능 | 제조사 |
74ACT18823MTD | 18-Bit D-Type Flip-Flop with 3-STATE Outputs | Fairchild Semiconductor |
DataSheet.kr | 2020 | 연락처 | 링크모음 | 검색 | 사이트맵 |