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What is 74ACTQ16240MTD?

This electronic component, produced by the manufacturer "Fairchild Semiconductor", performs the same function as "16-Bit Inverting Buffer/Line Driver with 3-STATE Outputs".


74ACTQ16240MTD Datasheet PDF - Fairchild Semiconductor

Part Number 74ACTQ16240MTD
Description 16-Bit Inverting Buffer/Line Driver with 3-STATE Outputs
Manufacturers Fairchild Semiconductor 
Logo Fairchild Semiconductor Logo 


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May 1991
Revised November 1998
74ACTQ16240
16-Bit Inverting Buffer/Line Driver with 3-STATE Outputs
General Description
The ACTQ16240 contains sixteen inverting buffers with 3-
STATE outputs designed to be employed as a memory and
address driver, clock driver, or bus-oriented transmitter/
receiver. The device is nibble controlled. Each nibble has
separate 3-STATE control inputs which can be shorted
together for full 16-bit operation.
The ACTQ16240 utilizes Fairchild’s Quiet Seriestechnol-
ogy to guarantee quiet output switching and improve
dynamic threshold performance. FACT Quiet Seriesfea-
tures GTOoutput control for superior performance.
Features
s Utilizes Fairchild’s FACT Quiet Series technology
s Guaranteed simultaneous switching noise level and
dynamic threshold performance
s Guaranteed pin-to-pin output skew
s Separate control logic for each byte
s 16-bit version of the ACTQ240
s Outputs source/sink 24 mA
s Additional specs for multiple output switching
s Output loading specs for both 50 pF and 250 pF loads
Ordering Code:
Order Number Package Number
Package Description
74ACTQ16240SSC
MS48A
48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300” Wide
74ACTQ16240MTD
MTD48
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Logic Symbol
Connection Diagram
Pin Assignment
for SSOP and TSSOP
Pin Descriptions
Pin Names
OEn
I0–I15
O0–O15
Description
Output Enable Inputs (Active Low)
Inputs
Outputs
FACT, FACT Quiet Series, Quiet Series, and GTOare trademarks of Fairchild Semiconductor Corporation.
© 1999 Fairchild Semiconductor Corporation DS010924.prf
www.fairchildsemi.com

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74ACTQ16240MTD equivalent
FACT Noise Characteristics
The setup of a noise characteristics measurement is critical
to the accuracy and repeatability of the tests. The following
is a brief description of the setup used to measure the
noise characteristics of FACT.
Equipment:
Hewlett Packard Model 8180A Word Generator
PC-163A Test Fixture
Tektronics Model 7854 Oscilloscope
Procedure:
1. Verify Test Fixture Loading: Standard Load 50 pF,
500.
2. Deskew the HFS generator so that no two channels
have greater than 150 ps skew between them. This
requires that the oscilloscope be deskewed first. It is
important to deskew the HFS generator channels
before testing. This will ensure that the outputs switch
simultaneously.
3. Terminate all inputs and outputs to ensure proper load-
ing of the outputs and that the input levels are at the
correct voltage.
4. Set the HFS generator to toggle all but one output at a
frequency of 1 MHz. Greater frequencies will increase
DUT heating and affect the results of the measure-
ment.
FIGURE 1. Quiet Output Noise Voltage Waveforms
Note 14: VOHV and VOLP are measured with respect to ground refer-
ence.
Note 15: Input pulses have the following characteristics: f = 1 MHz,
tr = 3 ns, tf = 3 ns, skew < 150 ps.
5. Set the HFS generator input levels at 0V LOW and 3V
HIGH for ACT devices and 0V LOW and 5V HIGH for
AC devices. Verify levels with an oscilloscope.
VOLP/VOLV and VOHP/VOHV:
• Determine the quiet output pin that demonstrates the
greatest noise levels. The worst case pin will usually be
the furthest from the ground pin. Monitor the output volt-
ages using a 50coaxial cable plugged into a standard
SMB type connector on the test fixture. Do not use an
active FET probe.
• Measure VOLP and VOLV on the quiet output during the
worst case transition for active and enable. Measure
VOHP and VOHV on the quiet output during the worst
case active and enable transition.
• Verify that the GND reference recorded on the oscillo-
scope has not drifted to ensure the accuracy and repeat-
ability of the measurements.
VILD and VIHD:
• Monitor one of the switching outputs using a 50coaxial
cable plugged into a standard SMB type connector on
the test fixture. Do not use an active FET probe.
• First increase the input LOW voltage level, VIL, until the
output begins to oscillate or steps out a min of 2 ns.
Oscillation is defined as noise on the output LOW level
that exceeds VIL limits, or on output HIGH levels that
exceed VIH limits. The input LOW voltage level at which
oscillation occurs is defined as VILD.
• Next decrease the input HIGH voltage level on the, VIH,
until the output begins to oscillate or steps out a mins of
2 ns. Oscillation is defined as noise on the output LOW
level that exceeds VIL limits, or on output HIGH levels
that exceed VIH limits. The input HIGH voltage level at
which oscillation occurs is defined as VIHD.
• Verify that the GND reference recorded on the oscillo-
scope has not drifted to ensure the accuracy and repeat-
ability of the measurements.
FIGURE 2. Simultaneous Switching Test Circuit
5 www.fairchildsemi.com


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74ACTQ16240MTDThe function is 16-Bit Inverting Buffer/Line Driver with 3-STATE Outputs. Fairchild SemiconductorFairchild Semiconductor

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