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부품번호 | 74ACTQ16373MTD 기능 |
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기능 | 16-Bit Transparent Latch with 3-STATE Outputs | ||
제조업체 | Fairchild Semiconductor | ||
로고 | |||
전체 8 페이지수
June 1991
Revised November 1999
74ACTQ16373
16-Bit Transparent Latch with 3-STATE Outputs
General Description
The ACTQ16373 contains sixteen non-inverting latches
with 3-STATE outputs and is intended for bus oriented
applications. The device is byte controlled. The flip-flops
appear transparent to the data when the Latch Enable (LE)
is HIGH. When LE is low, the data that meets the setup
time is latched. Data appears on the bus when the Output
Enable (OE) is LOW. When OE is HIGH, the outputs are in
high Z state. The ACTQ16373 utilizes Fairchild’s Quiet
Series technology to guarantee quiet output switching
and improved dynamic threshold performance. FACT Quiet
Series features GTO output control for superior perfor-
mance.
Features
s Utilizes Fairchild FACT Quiet Series technology
s Guaranteed simultaneous switching noise level and
dynamic threshold performance
s Guaranteed pin-to-pin output skew
s Separate control logic for each byte
s 16-bit version of the ACTQ373
s Outputs source/sink 24 mA
s Additional specs for Multiple Output Switching
s Output Loading specs for both 50 pF and 250 pF loads
Ordering Code:
Order Number Package Number
Package Description
74ACTQ16373MEA
MS48A
48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300” Wide
74ACTQ16373MTD
MTD48
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Logic Symbol
Connection Diagram
Pin Descriptions
Pin Names
OEn
LEn
I0–I15
O0–O15
Description
Output Enable Input (Active LOW)
Latch Enable Input
Inputs
Outputs
FACT, Quiet Series, FACT Quiet Series, and GTO are trademarks of Fairchild Semiconductor Corporation.
© 1999 Fairchild Semiconductor Corporation DS010934
www.fairchildsemi.com
AC Electrical Characteristics
Symbol
Parameter
tPLH Propagation Delay
tPHL
Dn to On
tPLH Propagation Delay
tPHL
LE to On
tPZH Output Enable
tPZL Delay
tPHZ Output Disable
tPLZ Delay
Note 8: Voltage Range 5.0 is 5.0V ± 0.5V.
VCC
(V)
(Note 8)
5.0
5.0
5.0
5.0
TA = +25°C
CL = 50 pF
Min Typ Max
3.1 5.3 7.9
2.6 4.6 7.3
3.1 5.4 7.9
2.8 4.9 7.3
2.5 4.7 7.4
2.7 4.8 7.5
2.1 5.1 7.9
2.0 4.5 7.4
TA = −40°C to +85°C
CL = 50 pF
Min Max
3.1 8.4
2.6 7.8
3.2 8.4
2.8 7.8
2.5 7.9
2.7 8.0
2.1 8.2
2.0 7.9
Units
ns
ns
ns
ns
Extended AC Electrical Characteristics
TA = −40°C to +85°C
TA = −40°C to +85°C
Symbol
Parameter
VCC
(V)
(Note 9)
CL = 50 pF
16 Outputs Switching
(Note 10)
CL = 250 pF
(Note 11)
Units
Min Max Min Max
tPLH
tPHL
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
tOSHL
(Note 14)
Propagation Delay
Data to Output
Propagation Delay
Latch Enable to Output
Output Enable
Time
Output Disable
Time
Pin to Pin Skew
HL Data to Output
5.0V
5.0V
5.0V
5.0V
5.0V
4.7
4.6
4.6
4.1
3.5
3.6
3.4
3.1
12.7
10.6
13.3
10.4
10.4
10.9
8.5
8.1
1.3
6.6 15.7
6.4 14.5
6.3 15.3
5.8 13.6
(Note 12)
(Note 13)
ns
ns
ns
ns
ns
tOSLH
(Note 14)
Pin to Pin Skew
LH Data to Output
5.0V
2.1
ns
tOST
(Note 14)
Pin to Pin Skew
LH/HL Data to Output
5.0V
4.0
ns
Note 9: Voltage Range 5.0 is 5.0V ± 0.5V.
Note 10: This specification is guaranteed but not tested. The limits apply to propagation delays for all paths described switching in phase
(i.e., all LOW-to-HIGH, HIGH-to-LOW, etc.).
Note 11: This specification is guaranteed but not tested. The limits represent propagation delays with 250 pF load capacitors in place of the 50 pF load
capacitors in the standard AC load. This specification pertains to single output switching only.
Note 12: 3-STATE delays are load dominated and have been excluded from the datasheet.
Note 13: The Output Disable Time is dominated by the RC Network (500Ω, 250 pF) on the output and has been excluded from the datasheet.
Note 14: Skew is defined as the absolute value of the difference between the actual propagation delays for any two separate outputs of the same device.
The specification applies to any outputs switching HIGH-to-LOW (tOSHL), LOW-to-HIGH (tOSLH), or any combination switching LOW-to-HIGH and/or HIGH-
to-LOW (tOST).
www.fairchildsemi.com
4
4페이지 Physical Dimensions inches (millimeters) unless otherwise noted
48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300” Wide
Package Number MS48A
7 www.fairchildsemi.com
7페이지 | |||
구 성 | 총 8 페이지수 | ||
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부품번호 | 상세설명 및 기능 | 제조사 |
74ACTQ16373MTD | 16-Bit Transparent Latch with 3-STATE Outputs | Fairchild Semiconductor |
DataSheet.kr | 2020 | 연락처 | 링크모음 | 검색 | 사이트맵 |