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74ACTQ16540MTD PDF 데이터시트 : 부품 기능 및 핀배열

부품번호 74ACTQ16540MTD
기능 16-Bit Inverting Buffer/Line Driver with 3-STATE Outputs
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74ACTQ16540MTD 데이터시트, 핀배열, 회로
May 1991
Revised November 1999
74ACTQ16540
16-Bit Inverting Buffer/Line Driver with 3-STATE Outputs
General Description
The ACTQ16540 contains sixteen inverting buffers with 3-
STATE outputs designed to be employed as a memory and
address driver, clock driver, or bus-oriented transmitter/
receiver. The device is byte controlled. Each byte has sep-
arate 3-STATE control inputs which can be shorted
together for full 16-bit operation.
The ACTQ16540 utilizes Fairchild Quiet Seriestechnol-
ogy to guarantee quiet output switching and improved
dynamic threshold performance. FACT Quiet Seriesfea-
tures GTOoutput control for superior performance.
Features
s Utilizes Fairchild FACT Quiet Series technology
s Guaranteed simultaneous switching noise level and
dynamic threshold performance
s Guaranteed pin-to-pin output skew
s Separate control logic for each byte
s Outputs source/sink 24 mA
s Additional specs for multiple output switching
s Output loading specs for both 50 pF and 250 pF loads
Ordering Code:
Order Number Package Number
Package Description
74ACTQ16540SSC
MS48A
48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300Wide
74ACTQ16540MTD
MTD48
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Device also available in Tape and Reel Specify by appending suffix letter “X” to the ordering code.
Logic Symbol
Connection Diagram
Pin Descriptions
Pin
Names
OEn
I0I15
O0O15
Description
Output Enable Input (Active LOW)
Inputs
Outputs
FACT, Quiet Series, FACT Quiet Seriesand GTOare trademarks of Fairchild Semiconductor Corporation.
© 1999 Fairchild Semiconductor Corporation DS010927
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74ACTQ16540MTD pdf, 반도체, 판매, 대치품
AC Electrical Characteristics
Symbol
Parameter
tPLH Propagation Delay
tPHL Data to Output
tPZH Output Enable
tPZL Time
tPHZ
Output Disable
tPLZ Time
Note 8: Voltage Range 5.0 is 5.0V ± 0.5V.
VCC
(V)
(Note 8)
5.0
5.0
5.0
TA = +25°C
CL = 50 pF
Typ Min Max
2.7 4.9 7.3
3.0 5.1 7.3
2.5 4.8 7.4
2.7 5.3 8.0
2.5 5.4 8.3
2.3 5.0 7.4
TA = −40°C to +85°C
CL = 50 pF
Min Max
2.7 7.8
3.0 7.8
2.5 7.9
2.7 8.5
2.5 8.7
2.3 7.9
Units
ns
ns
ns
Extended AC Electrical Characteristics
TA = −40°C to +85°C
CL = 50 pF
TA = −40°C to +85°C
Symbol
Parameter
VCC 16 Outputs Switching
CL = 250 pF
Units
(V) (Note 10)
(Note 11)
(Note 9)
Min
Typ
Max
Min
Max
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
tOSHL
(Note 14)
Propagation Delay,
Data to Output
Output Enable Time
Output Disable Time
Pin to Pin Skew,
HL Data to Output
4.0
5.0
4.0
3.2
5.0
3.4
3.8
5.0
3.1
5.0
12.6
10.0
10.8
10.8
9.5
9.2
1.2
5.6 15.5
5.6 13.6
(Note 12)
(Note 13)
ns
ns
ns
ns
tOSLH
Pin to Pin Skew,
5.0
2.5
ns
(Note 14) LH Data to Output
tOST
Pin to Pin Skew,
5.0
4.3
ns
(Note 14) LH/HL Data to Output
Note 9: Voltage Range 5.0 is 5.0V ± 0.5V.
Note 10: This specification is guaranteed but not tested. The limits apply to propagation delays for all paths described switching in phase (i.e., all LOW-to-
HIGH, HIGH-to-LOW, etc.).
Note 11: This specification is guaranteed but not tested. The limits represent propagation delays with 250 pF load capacitors in place of the 50 pF load
capacitors in the standard AC load. This specification pertains to single output switching only.
Note 12: 3-STATE delays are load dominated and have been excluded from the datasheet.
Note 13: The Output Disable Time is dominated by the RC network (500, 250 pF) on the output and has been excluded from the datasheet.
Note 14: Skew is defined as the absolute value of the difference between the actual propagation delays for any two separate outputs of the same device.
The specification applies to any outputs switching HIGH-to-LOW (tOSHL), LOW-to-HIGH (tOSLH), or any combination switching LOW-to-HIGH and/or HIGH-
to-LOW (tOST).
Capacitance
Symbol
CIN
CPD
Parameter
Input Pin Capacitance
Power Dissipation Capacitance
Typ Units
Conditions
4.5 pF VCC = 5.0V
30 pF VCC = 5.0V
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74ACTQ16540MTD 전자부품, 판매, 대치품
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Package Number MTD48
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILDS PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
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74ACTQ16540MTD

16-Bit Inverting Buffer/Line Driver with 3-STATE Outputs

Fairchild Semiconductor
Fairchild Semiconductor

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