74ACTQ16543SSC Datasheet PDF - Fairchild Semiconductor
| Part Number | 74ACTQ16543SSC | |
| Description | 16-Bit Registered Transceiver with 3-STATE Outputs | |
| Manufacturers | Fairchild Semiconductor | |
| Logo |  |
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December 1991
Revised December 1998
74ACTQ16543
16-Bit Registered Transceiver with 3-STATE Outputs
General Description
The ACTQ16543 contains sixteen non-inverting transceiv-
ers containing two sets of D-type registers for temporary
storage of data flowing in either direction. Each byte has
separate control inputs which can be shorted together for
full 16-bit operation. Separate Latch Enable and Output
Enable inputs are provided for each register to permit inde-
pendent input and output control in either direction of data
flow.
The ACTQ16543 utilizes Fairchild Quiet Series™ technol-
ogy to guarantee quiet output switching and improved
dynamic threshold performance. FACT Quiet Series™ fea-
tures GTO™ output control and undershoot corrector for
superior performance.
Features
s Utilizes Fairchild FACT Quiet Series technology
s Guaranteed simultaneous switching noise level and
dynamic threshold performance
s Guaranteed pin-to-pin output skew
s Independent registers for A and B buses
s Separate controls for data flow in each direction
s Back-to-back registers for storage
Multiplexed real-time and stored data transfers
s Separate control logic for each byte
s 16-bit version of the ACTQ543
s Outputs source/sink 24 mA
s Additional specs for Multiple Output Switching
s Output loading specs for both 50 pF and 250pF loads
Ordering Code:
Order Number Package Number
Package Description
74ACTQ16543SSC
MS56A
56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300” Wide
74ACTQ16543MTD
MTD56
56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Logic Symbol
Pin Descriptions
Pin Names
Descriptions
OEABn
OEBAn
CEABn
CEBAn
LEABn
LEBAn
A0–A15
A-to-B Output Enable Input (Active LOW)
B-to-A Output Enable Input (Active LOW)
A-to-B Enable Input (Active LOW)
B-to-A Enable Input (Active LOW)
A-to-B Latch Enable Input (Active LOW)
B-to-A Latch Enable Input (Active LOW)
A-to-B Data Inputs or
B-to-A 3-STATE Outputs
B0–B15
B-to-A Data Inputs or
A-to-B 3-STATE Outputs
FACT™, Quiet Series™, FACT Quiet Series™ and GTO™ are trademarks of Fairchild Semiconductor Corporation.
© 1999 Fairchild Semiconductor Corporation DS010967.prf
www.fairchildsemi.com
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DC Electrical Characteristics (Continued)
Note 5: Maximum number of outputs that can switch simultaneously is n. (n − 1) outputs are switched LOW and one output held LOW.
Note 6: Maximum number of outputs that can switch simultaneously is n. (n − 1) outputs are switched HIGH and one output held HIGH.
Note 7: Maximum number of data inputs (n) switching. (n − 1) inputs switching 0V to 3V Input under test switching 3V to threshold (VILD).
AC Electrical Characteristics
Symbol
Parameter
tPLH Propagation Delay
tPHL Transparent Mode
An to Bnor Bn to An
tPLH Propagation Delay
tPHL
LEBAn, LEABn
to An, Bn
tPZH Output Enable Time
tPZL OEBAn or OEABn to An or Bn
CEBAn or CEABn to An or Bn
tPHZ Output Disable Time
tPLZ OEBAn or OEABn to An or Bn
CEBAn or CEABn to An or Bn
Note 8: Voltage Range 5.0 is 5.0V ±0.5V.
VCC
(V)
(Note 8)
5.0
5.0
5.0
5.0
TA = +25°C
CL = 50 pF
Min Typ Max
3.8 5.9 8.3
3.5 5.5 7.9
4.7 6.9 9.8
3.9 6.3 9.0
4.2 6.3 9.2
4.9 7.3 10.3
2.8 5.2 8.0
2.6 5.0 7.6
TA = −40°C to +85°C
CL = 50 pF
Min Max
3.0 9.0
2.6 8.5
3.4 10.8
3.1 9.8
3.0 9.9
3.6 10.3
2.1 8.3
2.0 8.1
AC Operating Requirements
Symbol
Parameter
tS Setup Time, HIGH or LOW
An or Bn to LEBAn or LEABn
tH Hold Time, HIGH or LOW
An or Bn to LEBAn or LEABn
tW Latch Enable, B to A
Pulse Width, LOW
Note 9: Voltage Range 5.0 is 5.0V ±0.5V
VCC
(V)
(Note 9)
5.0
5.0
5.0
TA = +25°C
TA = −40°C to +85°C
CL = 50 pF
CL = 50 pF
Typ Guaranteed Minimum
3.0 3.0
1.5 1.5
4.0 4.0
Units
ns
ns
ns
ns
Units
ns
ns
ns
5 www.fairchildsemi.com
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