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부품번호 74ACTQ16543SSC 기능
기능 16-Bit Registered Transceiver with 3-STATE Outputs
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74ACTQ16543SSC 데이터시트, 핀배열, 회로
December 1991
Revised December 1998
74ACTQ16543
16-Bit Registered Transceiver with 3-STATE Outputs
General Description
The ACTQ16543 contains sixteen non-inverting transceiv-
ers containing two sets of D-type registers for temporary
storage of data flowing in either direction. Each byte has
separate control inputs which can be shorted together for
full 16-bit operation. Separate Latch Enable and Output
Enable inputs are provided for each register to permit inde-
pendent input and output control in either direction of data
flow.
The ACTQ16543 utilizes Fairchild Quiet Seriestechnol-
ogy to guarantee quiet output switching and improved
dynamic threshold performance. FACT Quiet Seriesfea-
tures GTOoutput control and undershoot corrector for
superior performance.
Features
s Utilizes Fairchild FACT Quiet Series technology
s Guaranteed simultaneous switching noise level and
dynamic threshold performance
s Guaranteed pin-to-pin output skew
s Independent registers for A and B buses
s Separate controls for data flow in each direction
s Back-to-back registers for storage
Multiplexed real-time and stored data transfers
s Separate control logic for each byte
s 16-bit version of the ACTQ543
s Outputs source/sink 24 mA
s Additional specs for Multiple Output Switching
s Output loading specs for both 50 pF and 250pF loads
Ordering Code:
Order Number Package Number
Package Description
74ACTQ16543SSC
MS56A
56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300” Wide
74ACTQ16543MTD
MTD56
56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Logic Symbol
Pin Descriptions
Pin Names
Descriptions
OEABn
OEBAn
CEABn
CEBAn
LEABn
LEBAn
A0–A15
A-to-B Output Enable Input (Active LOW)
B-to-A Output Enable Input (Active LOW)
A-to-B Enable Input (Active LOW)
B-to-A Enable Input (Active LOW)
A-to-B Latch Enable Input (Active LOW)
B-to-A Latch Enable Input (Active LOW)
A-to-B Data Inputs or
B-to-A 3-STATE Outputs
B0–B15
B-to-A Data Inputs or
A-to-B 3-STATE Outputs
FACT, Quiet Series, FACT Quiet Seriesand GTOare trademarks of Fairchild Semiconductor Corporation.
© 1999 Fairchild Semiconductor Corporation DS010967.prf
www.fairchildsemi.com




74ACTQ16543SSC pdf, 반도체, 판매, 대치품
Absolute Maximum Ratings(Note 1)
Supply Voltage (VCC)
DC Input Diode Current (IIK)
VI = −0.5V
VI = VCC + 0.5V
DC Output Diode Current (IOK)
VO = −0.5V
VO = VCC + 0.5V
DC Output Voltage (VO)
DC Output Source/Sink Current (IO)
DC VCC or Ground Current
per Output Pin
Storage Temperature
0.5V to +7.0V
20 mA
+20 mA
20 mA
+20 mA
0.5V to VCC + 0.5V
±50 mA
±50 mA
65°C to +150°C
Recommended Operating
Conditions
Supply Voltage (VCC)
Input Voltage (VI)
Output Voltage (VO)
Operating Temperature (TA)
Minimum Input Edge Rate (V/t)
4.5V to 5.5V
0V to VCC
0V to VCC
40°C to +85°C
125 mV/ns
VIN from 0.8V to 2.0V
VCC @ 4.5V, 5.5V
Note 1: Absolute maximum ratings are those values beyond which damage
to the device may occur. The databook specifications should be met, with-
out exception, to ensure that the system design is reliable over its power
supply, temperature, and output/input loading variables. Fairchild does not
recommend operation of FACTcircuits outside databook specifications.
DC Electrical Characteristics
Symbol
Parameter
VIH Minimum HIGH
Input Voltage
VIL Maximum LOW
Input Voltage
VOH Minimum HIGH
Output Voltage
VCC
(V)
4.5
5.5
4.5
5.5
4.5
5.5
TA = +25°C
TA = −40°C to+85°C
Typ Guaranteed Limits
1.5 2.0
2.0
1.5 2.0
2.0
1.5 0.8
0.8
1.5 0.8
0.8
4.49
4.4
4.4
5.49
5.4
5.4
VOL Maximum LOW
Output Voltage
4.5 3.86
5.5 4.86
4.5 0.001
0.1
5.5 0.001
0.1
3.76
4.76
0.1
0.1
4.5
5.5
IOZT
Maximum I/O
Leakage Current
5.5
IIN Maximum Input
Leakage Current
5.5
ICCT
ICC
Maximum ICC/Input
Max Quiescent
Supply Current
5.5 0.6
5.5
IOLD
IOHD
VOLP
VOLV
VOHP
Minimum Dynamic
Output Current (Note 3)
Quiet Output
Maximum Dynamic VOL
Quiet Output
Minimum Dynamic VOL
Maximum
Overshoot
5.5
5.0 0.5
5.0 0.5
5.0 VOH + 1.0
VOHV
VIHD
Minimum
VCC Droop
Minimum HIGH Dynamic
Input Voltage Level
5.0 VOH 1.0
5.0 1.7
VILD
Maximum LOW Dynamic
Input Voltage Level
5.0 1.2
Note 2: All outputs loaded; thresholds associated with output under test.
Note 3: Maximum test duration 2.0 ms; one output loaded at a time.
Note 4: Worst case package.
0.36
0.36
±0.5
±0.1
8.0
0.8
0.8
VOH + 1.5
VOH 1.8
2.0
0.8
0.44
0.44
±5.0
±1.0
1.5
80.0
75
75
Units
Conditions
V VOUT = 0.1V
or VCC 0.1V
V VOUT = 0.1V
or VCC 0.1V
V IOUT = −50 µA
VIN = VILor VIH
V IOH = 24 mA
IOH = 24 mA (Note 2)
V IOUT = 50 µA
VIN = VILor VIH
V IOL = 24 mA
IOL = 24 mA (Note 2)
µA VI = VIL, VIH
VO = VCC, GND
µA VI = VCC,
GND
mA VI = VCC 2.1V
µA VIN = VCC
or GND
mA VOLD = 1.65V Max
mA VOHD = 3.85V Min
V Figure 1, Figure 2
(Note 5)(Note 6)
V Figure 1, Figure 2
(Note 5)(Note 6)
V Figure 1, Figure 2
(Note 4)(Note 6)
V Figure 1, Figure 2
(Note 4)(Note 6)
V (Note 4)(Note 7)
V (Note 4)(Note 7)
www.fairchildsemi.com
4

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74ACTQ16543SSC 전자부품, 판매, 대치품
FACT Noise Characteristics
The setup of a noise characteristics measurement is critical
to the accuracy and repeatability of the tests. The following
is a brief description of the setup used to measure the
noise characteristics of FACT.
Equipment:
Hewlett Packard Model 8180A Word Generator
PC-163A Test Fixture
Tektronics Model 7854 Oscilloscope
Procedure:
1. Verify Test Fixture Loading: Standard Load 50 pF,
500.
2. Deskew the HFS generator so that no two channels
have greater than 150 ps skew between them. This
requires that the oscilloscope be deskewed first. It is
important to deskew the HFS generator channels
before testing. This will ensure that the outputs switch
simultaneously.
3. Terminate all inputs and outputs to ensure proper load-
ing of the outputs and that the input levels are at the
correct voltage.
4.
VOHV and VOLP are measured with respect to ground reference.
Input pulses have the following characteristics: f = 1 MHz, tr = 3 ns, tf
= 3 ns, skew < 150 ps.
FIGURE 1. Quiet Output Noise Voltage Waveforms
5. Set the HFS generator to toggle all but one output at a
frequency of 1 MHz. Greater frequencies will increase
DUT heating and effect the results of the measure-
ment.
6. Set the HFS generator input levels at 0V LOW and 3V
HIGH for ACT devices and 0V LOW and 5V HIGH for
AC devices. Verify levels with an oscilloscope.
VOLP/VOLV and VOHP/VOHV:
• Determine the quiet output pin that demonstrates the
greatest noise levels. The worst case pin will usually be
the furthest from the ground pin. Monitor the output volt-
ages using a 50coaxial cable plugged into a standard
SMB type connector on the test fixture. Do not use an
active FET probe.
• Measure VOLP and VOLVon the quiet output during the
worst case transition for active and enable. Measure
VOHP and VOHV on the quiet output during the worst
case for active and enable transition.
• Verify that the GND reference recorded on the oscillo-
scope has not drifted to ensure the accuracy and repeat-
ability of the measurements.
VILD and VIHD:
• Monitor one of the switching outputs using a 50coaxial
cable plugged into a standard SMB type connector on
the test fixture. Do not use an active FET probe.
• First increase the input LOW voltage level, VIL, until the
output begins to oscillate or steps out a min of 2 ns.
Oscillation is defined as noise on the output LOW level
that exceeds VIL limits, or on output HIGH levels that
exceed VIH limits. The input LOW voltage level at which
oscillation occurs is defined as VILD.
• Next decrease the input HIGH voltage level, VIH, until
the output begins to oscillate or steps out a min of 2 ns.
Oscillation is defined as noise on the output LOW level
that exceeds VIL limits, or on output HIGH levels that
exceed VIH limits. The input HIGH voltage level at which
oscillation occurs is defined as VIHD.
• Verify that the GND reference recorded on the oscillo-
scope has not drifted to ensure the accuracy and repeat-
ability on the measurements.
FIGURE 2. Simultaneous Switching Test Circuit
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부품번호상세설명 및 기능제조사
74ACTQ16543SSC

16-Bit Registered Transceiver with 3-STATE Outputs

Fairchild Semiconductor
Fairchild Semiconductor

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