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부품번호 74ACTQ18823SSC 기능
기능 18-Bit D-Type Flip-Flop with 3-STATE Outputs
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74ACTQ18823SSC 데이터시트, 핀배열, 회로
September 1991
Revised November 1999
74ACTQ18823
18-Bit D-Type Flip-Flop with 3-STATE Outputs
General Description
The ACTQ18823 contains eighteen non-inverting D-type
flip-flops with 3-STATE outputs and is intended for bus ori-
ented applications. The device is byte controlled. A buff-
ered clock (CP), Clear (CLR), Clock Enable (EN) and
Output Enable (OE) are common to each byte and can be
shorted together for full 18-bit operation.
The ACTQ18823 utilizes Fairchild’s Quiet Seriestechnol-
ogy to guarantee quiet output switching and improved
dynamic threshold performance. FACT Quiet Seriesfea-
tures GTOoutput control and undershoot corrector for
superior performance.
Features
s Utilizes Fairchild’s FACT Quiet Series technology
s Broadside pinout allows for easy board layout
s Guaranteed simultaneous switching noise level and
dynamic threshold performance
s Guaranteed pin-to-pin output skew
s Separate control logic for each byte
s Extra data width for wider address/data paths or buses
carrying parity
s Outputs source/sink 24 mA
s Additional specs for Multiple Output Switching
s Output loading specs for both 50 pF and 250 pF loads
Ordering Code:
Order Number Package Number
Package Description
74ACTQ18823SSC
MS56A
56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300Wide
74ACTQ18823MTD
MTD56
56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Device also available in Tape and Reel. Specify by appending suffix letter Xto the ordering code.
Logic Symbol
Pin Descriptions
Pin Names
OEn
CLRn
ENn
CPn
I0I17
O0O17
Description
Output Enable Input (Active LOW)
Clear (Active LOW)
Clock Enable (Active LOW)
Clock Pulse Input
Inputs
Outputs
FACT, Quiet Series, FACT Quiet Series, and GTOare trademarks of Fairchild Semiconductor Corporation.
© 1999 Fairchild Semiconductor Corporation DS010953
www.fairchildsemi.com




74ACTQ18823SSC pdf, 반도체, 판매, 대치품
Absolute Maximum Ratings(Note 2)
Supply Voltage (VCC)
DC Input Diode Current (IIK)
VI = −0.5V
VI = VCC +0.5V
DC Output Diode Current (IOK)
VO = −0.5V
VO = VCC +0.5V
DC Output Voltage (VO)
DC Output Source/Sink Current (IO)
DC VCC or Ground Current
Per Output Pin
Junction Temperature
PDIP/SOIC
Storage Temperature
ESD Last Passing Voltage (Min)
0.5V to +7.0V
20 mA
+20 mA
20 mA
+20 mA
0.5V to VCC + 0.5V
± 50 mA
± 50 mA
+140°C
65°C to +150°C
4000V
Recommended Operating
Conditions
Supply Voltage (VCC)
Input Voltage (VI)
Output Voltage (VO)
Operating Temperature (TA)
Minimum Input Edge Rate (V/t)
VIN from 0.8V to 2.0V
VCC @ 4.5V, 5.5V
4.5V to 5.5V
0V to VCC
0V to VCC
40°C to +85°C
125 mV/ns
Note 2: Absolute maximum ratings are those values beyond which damage
to the device may occur. The databook specifications should be met, with-
out exception, to ensure that the system design is reliable over its power
supply, temperature, and output/input loading variables. Fairchild does not
recommend operation of FACTcircuits outside databook specifications.
DC Electrical Characteristics
Symbol
Parameter
VCC
TA = +25°C
TA = −40°C to +85°C Units
(V) Typ
Guaranteed Limits
Conditions
VIH Minimum HIGH
Input Voltage
VIL Maximum LOW
Input Voltage
VOH Minimum HIGH
Output Voltage
4.5 1.5
5.5 1.5
4.5 1.5
5.5 1.5
4.5 4.49
5.5 5.49
2.0
2.0
0.8
0.8
4.4
5.4
2.0 V VOUT = 0.1V
2.0 or VCC 0.1V
0.8 V VOUT = 0.1V
0.8 or VCC 0.1V
4.4
5.4 V IOUT = −50 µA
VOL Maximum LOW
Output Voltage
4.5
5.5
4.5 0.001
5.5 0.001
3.86
4.86
0.1
0.1
3.76
4.76
0.1
0.1
VIN = VIL or VIH
V IOH = −24 mA
IOH = −24 mA (Note 3)
V IOUT = 50 µA
4.5 0.36
5.5 0.36
IOZ Maximum 3-STATE
Leakage Current
5.5 ±0.5
IIN Maximum Input Leakage Current
5.5
ICCT
Maximum ICC/Input
5.5 0.6
ICC Maximum Quiescent Supply Current
5.5
IOLD
IOHD
Minimum Dynamic
Output Current (Note 4)
5.5
VOLP
Quiet Output Maximum Dynamic VOL
5.0 0.5
VOLV
Quiet Output Minimum Dynamic VOL
5.0 0.5
VOHP Maximum Overshoot
5.0 VOH + 1.0
VOHV Minimum VCC Droop
5.0 VOH 1.0
VIHD
Minimum High Voltage Level
5.0 1.7
VILD Maximum Low Dynamic Input Voltage Level 5.0
1.2
Note 3: All outputs loaded; thresholds associated with output under test.
±0.1
8.0
0.8
0.8
VOH + 1.5
VOH 1.8
2.0
1.2
0.44
0.44
±5.0
±1.0
1.5
80.0
75
75
VIN = VIL or VIH
V IOL = 24 mA
IOL = 24 mA (Note 3)
µA VI = VIL, VIH
VO = VCC, GND
µA VI = VCC, GND
mA VI = VCC 2.1V
µA VIN = VCC or GND
mA VOLD = 1.65V Max
mA VOHD = 3.85V Min
V (Note 6)(Note 7)
V (Note 6)(Note 7)
V (Note 5)(Note 7)
V (Note 5)(Note 7)
V (Note 5)(Note 8)
V (Note 5)(Note 8)
Note 4: Maximum test duration 2.0 ms, one output loaded at a time.
Note 5: Worst case package.
Note 6: Maximum number of outputs that can switch simultaneously is n. (n 1) outputs are switched LOW and one output held LOW.
Note 7: Maximum number of outputs that can switch simultaneously is n. (n 1) outputs are switched HIGH and one output held HIGH.
Note 8: Maximum number of data inputs (n) switching. (n 1) input switching 0V to 3V. Input under test switching 3V to threshold (VILD).
www.fairchildsemi.com
4

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74ACTQ18823SSC 전자부품, 판매, 대치품
FACT Noise Characteristics
The setup of a noise characteristics measurement is critical
to the accuracy and repeatability of the tests. The following
is a brief description of the setup used to measure the
noise characteristics of FACT.
Equipment:
Hewlett Packard Model 8180A Word Generator
PC-163A Test Fixture
Tektronics Model 7854 Oscilloscope
Procedure:
1. Verify Test Fixture Loading: Standard Load 50 pF,
500.
2. Deskew the HFS generator so that no two channels
have greater than 150 ps skew between them. This
requires that the oscilloscope be deskewed first. It is
important to deskew the HFS generator channels
before testing. This will ensure that the outputs switch
simultaneously.
3. Terminate all inputs and outputs to ensure proper load-
ing of the outputs and that the input levels are at the
correct voltage.
4. Set the HFS generator to toggle all but one output at a
frequency of 1 MHz. Greater frequencies will increase
DUT heating and affect the results of the measure-
ment.
VOHV and VOLP are measured with respect to ground reference.
Input pulses have the following characteristics: f = 1 MHz, tr = 3 ns,
tf = 3 ns, skew < 150 ps.
FIGURE 1. Quiet Output Noise Voltage Waveforms
5. Set the HFS generator input levels at 0V LOW and 3V
HIGH for ACT devices and 0V LOW and 5V HIGH for
AC devices. Verify levels with an oscilloscope.
VOLP/VOLV and VOHP/VOHV:
Determine the quiet output pin that demonstrates the
greatest noise levels. The worst case pin will usually be
the furthest from the ground pin. Monitor the output volt-
ages using a 50coaxial cable plugged into a standard
SMB type connector on the test fixture. Do not use an
active FET probe.
Measure VOLP and VOLV on the quiet output during the
worst case transition for active and enable. Measure
VOHP and VOHV on the quiet output during the worst
case active and enable transition.
Verify that the GND reference recorded on the oscillo-
scope has not drifted to ensure the accuracy and repeat-
ability of the measurements.
VILD and VIHD:
Monitor one of the switching outputs using a 50coaxial
cable plugged into a standard SMB type connector on
the test fixture. Do not use an active FET probe.
First increase the input LOW voltage level, VIL, until the
output begins to oscillate or steps out a min of 2 ns.
Oscillation is defined as noise on the output LOW level
that exceeds VIL limits, or on output HIGH levels that
exceed VIH limits. The input LOW voltage level at which
oscillation occurs is defined as VILD.
Next decrease the input HIGH voltage level, VIH, until
the output begins to oscillator steps out a min of 2 ns.
Oscillation is defined as noise on the output LOW level
that exceeds VIL limits, or on output HIGH levels that
exceed VIH limits. The input HIGH voltage level at which
oscillation occurs is defined as VIHD.
Verify that the GND reference recorded on the oscillo-
scope has not drifted to ensure the accuracy and repeat-
ability of the measurements.
FIGURE 2. Simultaneous Switching Test Circuit
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74ACTQ18823SSC

18-Bit D-Type Flip-Flop with 3-STATE Outputs

Fairchild Semiconductor
Fairchild Semiconductor

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