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부품번호 74ACTQ18825MTD
기능 18-Bit Buffer/Line Driver with 3-STATE Outputs
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74ACTQ18825MTD 데이터시트, 핀배열, 회로
September 1991
Revised January 2000
74ACTQ18825
18-Bit Buffer/Line Driver with 3-STATE Outputs
General Description
The ACTQ18825 contains eighteen non-inverting buffers
with 3-STATE outputs designed to be employed as a mem-
ory and address driver, clock driver, or bus oriented trans-
mitter/receiver. The device is byte controlled. Each byte
has separate 3-STATE control inputs which can be shorted
together for full 18-bit operation.
The ACTQ18825 utilizes Fairchild FACT Quiet Series
technology to guarantee quiet output switching and
improved dynamic threshold performance. FACT Quiet
Series features GTOoutput control and undershoot cor-
rector for superior performance.
Features
s Utilizes Fairchild FACT Quiet Series technology
s Broadside pinout allows for easy board layout
s Guaranteed simultaneous switching noise level and
dynamic threshold performance
s Guaranteed pin-to-pin output skew
s Separate control logic for each byte
s Extra data width for wider address/data paths or buses
carrying parity
s Outputs source/sink 24 mA
s Additional specs for Multiple Output Switching
s Output loading specs for both 50 pF and 250 pF loads
Ordering Code:
Order Number Package Number
Package Description
74ACTQ18825SSC
MS56A
56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300” Wide
74ACTQ18825MTD
MTD56
56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Logic Symbol
Pin Descriptions
Pin Names
OEn
I0–I17
O0–O17
Description
Output Enable Input (Active LOW)
Inputs
Outputs
FACT, FACT Quiet Seriesand GTOare trademarks of Fairchild Semiconductor Corporation.
© 2000 Fairchild Semiconductor Corporation DS010955
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74ACTQ18825MTD pdf, 반도체, 판매, 대치품
AC Electrical Characteristics
Symbol
Parameter
tPHL Propagation Delay
tPLH Data to Output
tPZL Output Enable
tPZH
Time
tPLZ Output Disable
tPHZ
Time
Note 8: Voltage Range 5.0 is 5.0V ± 0.5V.
VCC
(V)
(Note 8)
5.0
5.0
5.0
TA = +25°C
CL = 50 pF
Min Typ Max
2.0 5.3 8.4
2.0 5.6 8.7
2.0 6.3 9.6
2.0 6.5 9.7
1.5 4.5 7.3
1.5 5.1 8.5
TA = −40°C to +85°C
CL = 50 pF
Min Max
2.0 9.0
2.0 9.2
2.0 10.3
2.0 10.4
1.5 7.6
1.5 8.8
Units
ns
ns
ns
Extended AC Electrical Characteristics
TA = −40°C to +85°C
TA = −40°C to +85°C
VCC = Com
VCC = Com
Symbol
Parameter
CL = 50 pF
16 Outputs Switching
CL = 250 pF
Units
(Note 9)
(Note 10)
Min Typ Max Min Max
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
tOSHL
(Note 13)
Propagation Delay
Data to Output
Output Enable Time
Output Disable Time
Pin to Pin Skew
HL Data to Output
6.5 8.0 9.8
5.5 6.5 8.9
6.1 7.6 9.2
6.5 7.8 9.4
3.1 5.0 6.1
3.5 5.2 6.5
1.5
(Note 11)
(Note 12)
ns
ns
ns
ns
tOSLH
(Note 13)
Pin to Pin Skew
LH Data to Output
2.0 ns
tOST
(Note 13)
Pin to Pin Skew
LH/HL Data to Output
2.0 ns
Note 9: This specification is guaranteed but not tested. The limits apply to propagation delays for all paths described switching in phase
(i.e., all LOW-to-HIGH, HIGH-to-LOW, etc.).
Note 10: This specification is guaranteed but not tested. The limits represent propagation delays with 250 pF load capacitors in place of the 50 pF load
capacitors in the standard AC load. This specification pertains to single output switching only.
Note 11: 3-STATE delays are load dominated and have been excluded from the datasheet.
Note 12: The Output Disable Time is dominated by the RC network (500, 250 pF) on the output and has been excluded from the datasheet.
Note 13: Skew is defined as the absolute value of the difference between the actual propagation delays for any two separate outputs of the same device.
The specification applies to any outputs switching HIGH-to-LOW (tOSHL), LOW-to-HIGH (tOSLH), or any combination switching LOW-to-HIGH and/or HIGH-
to-LOW (tOST).
Capacitance
Symbol
CIN
CPD
Parameter
Input Pin Capacitance
Power Dissipation Capacitance
Typ Units
Conditions
4.5 pF VCC = 5.0V
95 pF VCC = 5.0V
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74ACTQ18825MTD 전자부품, 판매, 대치품
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Package Number MTD56
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
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74ACTQ18825MTD

18-Bit Buffer/Line Driver with 3-STATE Outputs

Fairchild Semiconductor
Fairchild Semiconductor

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